diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 22c1d50c5..6f85dfb47 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1834,8 +1834,7 @@ class LiteXSoC(SoC):
             # Use PHY's eth_tx/eth_rx clock domains.
             ethcore = ClockDomainsRenamer({
                 "eth_tx": phy_cd + "_tx",
-                "eth_rx": phy_cd + "_rx",
-                "sys":    phy_cd + "_rx"})(ethcore)
+                "eth_rx": phy_cd + "_rx"})(ethcore)
         self.add_module(name=f"ethcore_{name}", module=ethcore)
 
         etherbone_cd = "sys"