From 13c57e8304d8c685268be67400a66a5f7c08c4a2 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
Date: Wed, 7 Feb 2024 07:20:31 +0100
Subject: [PATCH] soc/integration/soc: add_etherbone/ClockDomainRenamer: keep
 sys connected to sys instead of eth rx

---
 litex/soc/integration/soc.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 22c1d50c5..6f85dfb47 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1834,8 +1834,7 @@ class LiteXSoC(SoC):
             # Use PHY's eth_tx/eth_rx clock domains.
             ethcore = ClockDomainsRenamer({
                 "eth_tx": phy_cd + "_tx",
-                "eth_rx": phy_cd + "_rx",
-                "sys":    phy_cd + "_rx"})(ethcore)
+                "eth_rx": phy_cd + "_rx"})(ethcore)
         self.add_module(name=f"ethcore_{name}", module=ethcore)
 
         etherbone_cd = "sys"