From 13d75d3933bd731d2afe3b3134be64bf23a0f120 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 15 Dec 2014 19:33:38 +0100 Subject: [PATCH] move Counter to common and use it in all modules --- lib/sata/bist.py | 17 ++--------- lib/sata/common.py | 13 ++++++++- lib/sata/link/cont.py | 16 +++++----- lib/sata/transport/__init__.py | 53 +++++++++++----------------------- 4 files changed, 40 insertions(+), 59 deletions(-) diff --git a/lib/sata/bist.py b/lib/sata/bist.py index 746cf7d40..e6539736f 100644 --- a/lib/sata/bist.py +++ b/lib/sata/bist.py @@ -4,16 +4,6 @@ from migen.genlib.fsm import FSM, NextState from lib.sata.common import * from lib.sata.link.scrambler import Scrambler -@DecorateModule(InsertReset) -@DecorateModule(InsertCE) -class Counter(Module): - def __init__(self, width, signal=None, reset=0): - if signal is None: - self.value = Signal(width, reset=reset) - else: - self.value = signal - self.sync += self.value.eq(self.value+1) - class SATABIST(Module): def __init__(self, sector_size=512, max_count=1): self.sink = sink = Sink(command_rx_description(32)) @@ -25,10 +15,9 @@ class SATABIST(Module): self.ctrl_errors = Signal(32) self.data_errors = Signal(32) - - counter = Counter(32) - ctrl_error_counter = Counter(32, self.ctrl_errors) - data_error_counter = Counter(32, self.data_errors) + counter = Counter(bits_sign=32) + ctrl_error_counter = Counter(self.ctrl_errors, bits_sign=32) + data_error_counter = Counter(self.data_errors, bits_sign=32) self.submodules += counter, data_error_counter, ctrl_error_counter scrambler = InsertReset(Scrambler()) diff --git a/lib/sata/common.py b/lib/sata/common.py index 2c1e61f20..5024a7abc 100644 --- a/lib/sata/common.py +++ b/lib/sata/common.py @@ -179,4 +179,15 @@ def command_rx_data_description(dw): layout = [ ("data", dw) ] - return EndpointDescription(layout, packetized=True) \ No newline at end of file + return EndpointDescription(layout, packetized=True) + +@DecorateModule(InsertReset) +@DecorateModule(InsertCE) +class Counter(Module): + def __init__(self, signal=None, **kwargs): + if signal is None: + self.value = Signal(**kwargs) + else: + self.value = signal + self.width = flen(self.value) + self.sync += self.value.eq(self.value+1) diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py index ea56279cf..731ef9a54 100644 --- a/lib/sata/link/cont.py +++ b/lib/sata/link/cont.py @@ -13,7 +13,9 @@ class SATACONTInserter(Module): # Detect consecutive primitives # tn insert CONT - cnt = Signal(2) + counter = Counter(max=4) + self.submodules += counter + is_primitive = Signal() last_was_primitive = Signal() last_primitive = Signal(32) @@ -27,9 +29,9 @@ class SATACONTInserter(Module): self.comb += [ is_primitive.eq(sink.charisk != 0), change.eq((sink.data != last_primitive) | ~is_primitive), - cont_insert.eq(~change & (cnt==1)), - scrambler_insert.eq(~change & (cnt==2)), - last_primitive_insert.eq((cnt==2) & ( + cont_insert.eq(~change & (counter.value == 1)), + scrambler_insert.eq(~change & (counter.value == 2)), + last_primitive_insert.eq((counter.value == 2) & ( (~is_primitive & last_was_primitive) | (is_primitive & (last_primitive == primitives["HOLD"]) & (last_primitive != sink.data)))) ] @@ -44,11 +46,9 @@ class SATACONTInserter(Module): last_was_primitive.eq(0) ), If(change | last_primitive_insert_d, - cnt.eq(0) + counter.reset.eq(1) ).Else( - If(~scrambler_insert, - cnt.eq(cnt+1) - ) + counter.ce.eq(~scrambler_insert) ) ) diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index f95fb3935..843791fd8 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -30,11 +30,10 @@ class SATATransportTX(Module): cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - cnt = Signal(max=cmd_ndwords+1) - clr_cnt = Signal() - inc_cnt = Signal() + counter = Counter(max=cmd_ndwords+1) + self.submodules += counter - cmd_len = Signal(flen(cnt)) + cmd_len = Signal(counter.width) cmd_with_data = Signal() cmd_send = Signal() @@ -48,7 +47,7 @@ class SATATransportTX(Module): self.submodules += fsm fsm.act("IDLE", - clr_cnt.eq(1), + counter.reset.eq(1), If(sink.stb & sink.sop, If(test_type("REG_H2D"), NextState("SEND_REG_H2D_CMD") @@ -94,11 +93,11 @@ class SATATransportTX(Module): self.comb += \ If(cmd_send, link.sink.stb.eq(sink.stb), - link.sink.sop.eq(cnt==0), - link.sink.eop.eq((cnt==cmd_len) & ~cmd_with_data), - Case(cnt, cmd_cases), - inc_cnt.eq(sink.stb & link.sink.ack), - cmd_done.eq((cnt==cmd_len) & link.sink.stb & link.sink.ack) + link.sink.sop.eq(counter.value == 0), + link.sink.eop.eq((counter.value == cmd_len) & ~cmd_with_data), + Case(counter.value, cmd_cases), + counter.ce.eq(sink.stb & link.sink.ack), + cmd_done.eq((counter.value == cmd_len) & link.sink.stb & link.sink.ack) ).Elif(data_send, link.sink.stb.eq(sink.stb), link.sink.sop.eq(0), @@ -106,13 +105,6 @@ class SATATransportTX(Module): link.sink.d.eq(sink.data), ) - self.sync += \ - If(clr_cnt, - cnt.eq(0) - ).Elif(inc_cnt, - cnt.eq(cnt+1) - ) - def _decode_cmd(signal, description, obj): r = [] for k, v in sorted(description.items()): @@ -131,11 +123,10 @@ class SATATransportRX(Module): cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - cnt = Signal(max=cmd_ndwords+1) - clr_cnt = Signal() - inc_cnt = Signal() + counter = Counter(max=cmd_ndwords+1) + self.submodules += counter - cmd_len = Signal(flen(cnt)) + cmd_len = Signal(counter.width) cmd_receive = Signal() data_receive = Signal() @@ -151,7 +142,7 @@ class SATATransportRX(Module): data_sop = Signal() fsm.act("IDLE", - clr_cnt.eq(1), + counter.reset.eq(1), If(link.source.stb & link.source.sop, If(test_type("REG_D2H"), NextState("RECEIVE_REG_D2H_CMD") @@ -231,24 +222,14 @@ class SATATransportRX(Module): cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)] self.comb += \ - If(cmd_receive, - If(link.source.stb, - inc_cnt.eq(1), - ).Else( - inc_cnt.eq(0) - ) + If(cmd_receive & link.source.stb, + counter.ce.eq(1) ) self.sync += \ If(cmd_receive, - Case(cnt, cmd_cases), + Case(counter.value, cmd_cases), ) - self.sync += \ - If(clr_cnt, - cnt.eq(0) - ).Elif(inc_cnt, - cnt.eq(cnt+1) - ) - self.comb += cmd_done.eq((cnt==cmd_len) & link.source.ack) + self.comb += cmd_done.eq((counter.value == cmd_len) & link.source.ack) self.comb += link.source.ack.eq(cmd_receive | (data_receive & source.ack)) class SATATransport(Module):