From d494e3016621927eca7ffeccf119ca7c994d4f1d Mon Sep 17 00:00:00 2001 From: Radek Pesina Date: Fri, 11 Aug 2023 16:52:25 +1000 Subject: [PATCH] soc/cores/spi_mmap: Fix clock divider --- litex/soc/cores/spi/spi_mmap.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py index 77ced6bcd..7ef213137 100644 --- a/litex/soc/cores/spi/spi_mmap.py +++ b/litex/soc/cores/spi/spi_mmap.py @@ -124,7 +124,7 @@ class SPIMaster(LiteXModule): self.sync += [ If(clk_enable, clk_count.eq(clk_count + 1), - If(clk_count == self.clk_divider[2:], + If(clk_count == self.clk_divider[1:], clk.eq(~clk), clk_count.eq(0) ),