From 146068b0485921aa0e57e7c24ccca55226c418cc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Nov 2020 10:06:45 +0100 Subject: [PATCH] integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled. This prevents adding peripherals that requires IRQ support to SoC not supporting them. Enabling is done automatically when a CPU with interrupt support is added, but this can also be added manually. --- litex/soc/integration/soc.py | 18 +++++++++++++++++- litex/tools/litex_sim.py | 6 ++++-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 31bef380c..3dd9b5d45 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -619,6 +619,7 @@ class SoCIRQHandler(SoCLocHandler): SoCLocHandler.__init__(self, "IRQ", n_locs=n_irqs) self.logger = logging.getLogger("SoCIRQHandler") self.logger.info("Creating IRQ Handler...") + self.enabled = False # Check IRQ Number if n_irqs > 32: @@ -636,6 +637,19 @@ class SoCIRQHandler(SoCLocHandler): self.logger.info("IRQ Handler {}.".format(colorer("created", color="green"))) + # Enable --------------------------------------------------------------------------------------- + def enable(self): + self.enabled = True + + # Add ------------------------------------------------------------------------------------------ + def add(self, *args, **kwargs): + if self.enabled: + SoCLocHandler.add(self, *args, **kwargs) + else: + self.logger.error("Attempted to add an {} but SoC does not support {}.".format( + colorer("IRQ", color="red"), colorer("IRQs"))) + raise + # Str ------------------------------------------------------------------------------------------ def __str__(self): r ="IRQ Handler (up to {} Locations).\n".format(colorer(self.n_locs)) @@ -858,6 +872,7 @@ class SoC(Module): self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus) self.csr.add("cpu", use_loc_if_exists=True) if hasattr(self.cpu, "interrupt"): + self.irq.enable() for name, loc in self.cpu.interrupts.items(): self.irq.add(name, loc) self.add_config("CPU_HAS_INTERRUPT") @@ -1318,7 +1333,8 @@ class LiteXSoC(SoC): ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) self.csr.add(name, use_loc_if_exists=True) - self.add_interrupt(name) + if hasattr(self.cpu, "interrupt"): + self.irq.add(name, use_loc_if_exists=True) # Timing constraints if hasattr(phy, "crg"): eth_rx_clk = phy.crg.cd_eth_rx.clk diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index ca126931d..1154e41d5 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -236,7 +236,8 @@ class SimSoC(SoCCore): self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") - self.add_interrupt("ethmac") + if hasattr(self.cpu, "interrupt"): + self.irq.add("ethmac", use_loc_if_exists=True) # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) @@ -261,7 +262,8 @@ class SimSoC(SoCCore): self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") - self.add_interrupt("ethmac") + if hasattr(self.cpu, "interrupt"): + self.irq.add("ethmac", use_loc_if_exists=True) # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: