From 14a640302c3f36562ad0666b083026fd0ce20a97 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 25 Jun 2024 17:39:26 +0200 Subject: [PATCH] integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161. --- litex/soc/integration/soc.py | 27 ++++++++++++++++++++++++--- litex/tools/litex_sim.py | 26 +++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index e9aaa4471..2a522859a 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1871,10 +1871,31 @@ class LiteXSoC(SoC): "eth_tx": phy_cd + "_tx", "eth_rx": phy_cd + "_rx"})(ethmac) self.add_module(name=name, module=ethmac) + # Compute Regions size and add it to the SoC. - ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant - ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False) - self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) + ethmac_rx_region_size = ethmac.rx_slots.constant*ethmac.slot_size.constant + ethmac_tx_region_size = ethmac.tx_slots.constant*ethmac.slot_size.constant + ethmac_region_size = ethmac_rx_region_size + ethmac_tx_region_size + self.bus.add_region(name, SoCRegion( + origin = self.mem_map.get(name, None), + size = ethmac_region_size, + linker = True, + cached = False, + )) + ethmac_rx_region = SoCRegion( + origin = self.bus.regions[name].origin + 0, + size = ethmac_rx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name=f"{name}_rx", slave=ethmac.bus_rx, region=ethmac_rx_region) + ethmac_tx_region = SoCRegion( + origin = self.bus.regions[name].origin + ethmac_rx_region_size, + size = ethmac_tx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name=f"{name}_tx", slave=ethmac.bus_tx, region=ethmac_tx_region) # Add IRQs (if enabled). if self.irq.enabled: diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index ac0a28c38..1baa4ffb4 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -262,9 +262,29 @@ class SimSoC(SoCCore): interface = "wishbone", endianness = self.cpu.endianness ) - ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant - ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) - self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) + ethmac_rx_region_size = ethmac.rx_slots.constant*ethmac.slot_size.constant + ethmac_tx_region_size = ethmac.tx_slots.constant*ethmac.slot_size.constant + ethmac_region_size = ethmac_rx_region_size + ethmac_tx_region_size + self.bus.add_region("ethmac", SoCRegion( + origin = self.mem_map.get("ethmac", None), + size = ethmac_region_size, + linker = True, + cached = False, + )) + ethmac_rx_region = SoCRegion( + origin = self.bus.regions["ethmac"].origin + 0, + size = ethmac_rx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name="ethmac_rx", slave=ethmac.bus_rx, region=ethmac_rx_region) + ethmac_tx_region = SoCRegion( + origin = self.bus.regions["ethmac"].origin + ethmac_rx_region_size, + size = ethmac_tx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name="ethmac_tx", slave=ethmac.bus_tx, region=ethmac_tx_region) # Add IRQs (if enabled). if self.irq.enabled: