From 975cc9ecdc02dd96b2a1741dd5d573d3a33ae879 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 25 Jan 2023 20:47:30 +0100 Subject: [PATCH] soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY --- litex/soc/cores/clock/gowin_gw1n.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/clock/gowin_gw1n.py b/litex/soc/cores/clock/gowin_gw1n.py index bedc4f9b5..c6a9ab462 100644 --- a/litex/soc/cores/clock/gowin_gw1n.py +++ b/litex/soc/cores/clock/gowin_gw1n.py @@ -175,16 +175,16 @@ class GW1NPLL(Module): p_CLKOUTD3_SRC = "CLKOUT", # Recopy CLKOUT to CLKOUTD3. # Inputs. - i_CLKIN = self.clkin, # Clk Input. - i_CLKFB = 0, # Clk Feedback. - i_RESET = self.reset, # PLL Reset. - i_RESET_P = 0, # PLL Power Down. - i_ODSEL = 0, # Dynamic ODIV control. - i_FBDSEL = 0, # Dynamic IDIV control. - i_IDSEL = 0, # Dynamic FDIV control. - i_PSDA = 0, # Dynamic phase control. - i_DUTYDA = 0, # Dynamic duty cycle control. - i_FDLY = 0, # Dynamic CLKOUTP delay control. + i_CLKIN = self.clkin, # Clk Input. + i_CLKFB = 0, # Clk Feedback. + i_RESET = self.reset, # PLL Reset. + i_RESET_P = 0, # PLL Power Down. + i_ODSEL = Constant(0, 6), # Dynamic ODIV control. + i_FBDSEL = Constant(0, 6), # Dynamic IDIV control. + i_IDSEL = Constant(0, 6), # Dynamic FDIV control. + i_PSDA = Constant(0, 4), # Dynamic phase control. + i_DUTYDA = Constant(0, 4), # Dynamic duty cycle control. + i_FDLY = Constant(0, 4), # Dynamic CLKOUTP delay control. ) if self.device.startswith('GW1NS'): instance_name = 'PLLVR'