From 1610c643f91888c7c366599aa468a7ca591ac4d4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 20 Jan 2023 13:36:06 +0100 Subject: [PATCH] cpu/vexriscv_smp/core: Take into account wishbone_force_32b No Direct Memory Bus error. --- litex/soc/cores/cpu/vexriscv_smp/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index ed63ef603..48370f6e9 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -487,8 +487,8 @@ class VexRiscvSMP(CPU): # When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus. if len(self.memory_buses) == 0: - if VexRiscvSMP.with_fpu and not VexRiscvSMP.wishbone_memory: - raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.") + if VexRiscvSMP.with_fpu and (not VexRiscvSMP.wishbone_memory and not VexRiscvSMP.wishbone_force_32b): + raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory or --wishbone-force-32b to your build command.") else: VexRiscvSMP.wishbone_memory = True