From 16133359d6ba9d37c88e4107e12d228c26c8717f Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 18:13:46 +0100 Subject: [PATCH] soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width) --- litex/soc/integration/soc.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 7e5588658..bdcce774c 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1482,10 +1482,10 @@ class LiteXSoC(SoC): self.check_if_exists(name) uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate) uartbone = uart.UARTBone( - phy = uartbone_phy, - clk_freq = clk_freq, - cd = cd, - addr_width = self.bus.address_width) + phy = uartbone_phy, + clk_freq = clk_freq, + cd = cd, + address_width = self.bus.address_width) self.add_module(name=f"{name}_phy", module=uartbone_phy) self.add_module(name=name, module=uartbone) self.bus.add_master(name=name, master=uartbone.wishbone)