diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index 64cf1c2e1..113935770 100644
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -85,7 +85,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
         # Internal Tristate.
         if internal:
             if isinstance(pads, Record):
-                pads = pads.raw_bits()
+                pads = pads.flatten()
             # Proper inout IOs.
             for i in range(nbits):
                 t = TSTriple()