From 16a43e983ed32e140bd19ab3263bc1161c610460 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 30 Nov 2021 15:48:34 +0100
Subject: [PATCH] cores/gpio/GPIOTristate: Use Record.flatten() instead of
 Record.raw_bits().

Fix verilog syntax error.
---
 litex/soc/cores/gpio.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index 64cf1c2e1..113935770 100644
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -85,7 +85,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
         # Internal Tristate.
         if internal:
             if isinstance(pads, Record):
-                pads = pads.raw_bits()
+                pads = pads.flatten()
             # Proper inout IOs.
             for i in range(nbits):
                 t = TSTriple()