diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 6df91378e..94877dddf 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -30,6 +30,7 @@
 
 import os
 import sys
+from shutil import copyfile
 from migen import *
 
 from litex import get_data_mod
@@ -110,6 +111,11 @@ class BlackParrotRV64(CPU):
             o_wbm_bte_o  = idbus.bte,
         )
 
+        # Copy config loader to /tmp
+        vdir = get_data_mod("cpu", "blackparrot").data_location
+        bp_litex = os.path.join(vdir, "bp_litex")
+        copyfile(os.path.join(bp_litex, "cce_ucode.mem"), "/tmp/cce_ucode.mem")
+
         # Add Verilog sources
         try:
             os.environ["BP"]
diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index 97cb13910..20280eb03 100755
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -19,6 +19,3 @@ export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
 sed -i "s/localparam dram_base_addr_gp         = 40'h00_8000_0000;/localparam dram_base_addr_gp         = 40'h00_7000_0000;/" $BP_COMMON_DIR/src/include/bp_common_pkg.vh
 sed -i "s/localparam bp_pc_entry_point_gp=39'h00_8000_0000/localparam bp_pc_entry_point_gp=39'h00_7000_0000/" $BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
 sed -i "s/wire local_cmd_li        = (cmd_fifo_selected_lo.header.addr < dram_base_addr_gp);/wire local_cmd_li        = (cmd_fifo_selected_lo.header.addr < 32'h5000_0000);/" $BP_TOP_DIR/src/v/bp_softcore.v
-
-## Copy config loader to /tmp
-cp $BP_LITEX_DIR/cce_ucode.mem /tmp/.