From 16ba646b1b3e7c95ec8ae4ff8dabb4c203f28adc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 14 Nov 2015 03:15:10 +0100 Subject: [PATCH] add TODOs --- litex/gen/fhdl/verilog.py | 1 + litex/soc/interconnect/stream_packet.py | 5 ++++- litex/soc/interconnect/stream_sim.py | 5 +++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index b5bc3f562..faac18d1a 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -9,6 +9,7 @@ from litex.gen.fhdl.bitcontainer import bits_for from litex.gen.fhdl.namer import build_namespace from litex.gen.fhdl.conv_output import ConvOutput +# TODO: clean up simulation hack _reserved_keywords = { "always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1", diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index 17c724c44..cf2309c7b 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -5,7 +5,8 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect.stream import * -# TODO: move reverse_bytes / Counter +# TODO: clean up code below +# XXX def reverse_bytes(signal): n = (len(signal)+7)//8 @@ -379,3 +380,5 @@ class Buffer(Module): if almost_full is not None: self.almost_full = Signal() self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full) + +# XXX diff --git a/litex/soc/interconnect/stream_sim.py b/litex/soc/interconnect/stream_sim.py index 543f8d087..ba345f64f 100644 --- a/litex/soc/interconnect/stream_sim.py +++ b/litex/soc/interconnect/stream_sim.py @@ -5,6 +5,9 @@ from copy import deepcopy from litex.gen import * from litex.soc.interconnect.stream import Sink, Source +# TODO: clean up code below +# XXX + def print_with_prefix(s, prefix=""): if not isinstance(s, str): s = s.__repr__() @@ -191,3 +194,5 @@ class AckRandomizer(Module): selfp.run = 0 else: selfp.run = 1 + +# XXX \ No newline at end of file