From c8a9f205e0cd44e7eac1f3d2ccc57e955a0c3b2d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 21:06:25 +0100 Subject: [PATCH 1/3] soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion) --- litex/soc/cores/clock/efinix.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index fae23d7d4..9dd61647d 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule): self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset) self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked")) - def register_clkin(self, clkin, freq, name="", lvds_input=False): + def register_clkin(self, clkin, freq, name="", refclk_name="", lvds_input=False): block = self.platform.toolchain.ifacewriter.get_block(self.name) block["input_clock_name"] = self.platform.get_pin_name(clkin) @@ -81,6 +81,7 @@ class EFINIXPLL(LiteXModule): block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX" block["input_clock_pad"] = pin_name + block["input_refclk_name"] = refclk_name block["resource"] = pll_res block["clock_no"] = clock_no self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) From cbba5b46e948976ef16ca609740a456c1d8b5426 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 21:59:42 +0100 Subject: [PATCH 2/3] build/efinix/efinity: fix 90 phase shift float -> int (yes: WHY?) --- litex/build/efinix/efinity.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/build/efinix/efinity.py b/litex/build/efinix/efinity.py index 9e2592e01..04f6df610 100644 --- a/litex/build/efinix/efinity.py +++ b/litex/build/efinix/efinity.py @@ -280,6 +280,7 @@ class EfinityToolchain(GenericToolchain): # FIXME: peri.xml is generated from Efinity, why does it require patching? tools.replace_in_file(f"{self._build_name}.peri.xml", 'adv_out_phase_shift="0.0"', 'adv_out_phase_shift="0"') + tools.replace_in_file(f"{self._build_name}.peri.xml", 'adv_out_phase_shift="90.0"', 'adv_out_phase_shift="90"') def build_script(self): return "" # not used From fecc0cb2271a0b37af13ff77c02fd6fc8ba23b03 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 21:04:35 +0100 Subject: [PATCH 3/3] build/efinix/ifacewriter: PLL/LVDS serdes: Trion support --- litex/build/efinix/ifacewriter.py | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index 95177b2c1..5dc9f59dd 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -278,9 +278,18 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name) if block["input_clock"] == "LVDS_RX": - cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \ - .format(name, block["resource"], block["input_clock_pad"], block["clock_no"]) - cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name) + if block["version"] == "V3": + cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \ + .format(name, block["resource"], block["input_clock_pad"], block["clock_no"]) + cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name) + + else: + cmd += 'design.set_property("{}","EXT_CLK","EXT_CLK{}","PLL")\n'.format(name, block["clock_no"]) + # FIXME: pll feedback + cmd += 'design.set_property("{}","FEEDBACK_MODE","INTERNAL","PLL")\n'.format(name) + cmd += 'design.assign_resource("{}","{}","PLL")\n'.format(name, block["resource"]) + + elif block["input_clock"] == "EXTERNAL": # PLL V1 has a different configuration if partnumber[0:2] in ["T4", "T8"]: @@ -410,13 +419,12 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd.append('design.set_property("{}", "TX_DIFF_TYPE", "LVDS", "{}")'.format(name, block_type)) cmd.append('design.set_property("{}", "TX_HALF_RATE", "{}", "{}")'.format(name, half_rate, block_type)) cmd.append('design.set_property("{}", "TX_PRE_EMP", "MEDIUM_LOW", "{}")'.format(name, block_type)) - cmd.append('design.set_property("{}", "TX_SER", "{}", "{}")'.format(name, size, block_type)) cmd.append('design.set_property("{}", "TX_VOD", "TYPICAL", "{}")'.format(name, block_type)) else: cmd.append('design.set_property("{}","TX_OUTPUT_LOAD","3","{}")'.format(name, block_type)) cmd.append('design.set_property("{}","TX_REDUCED_SWING","0","{}")'.format(name, block_type)) cmd.append('design.set_property("{}","TX_SLOWCLK_DIV","1","{}")'.format(name, block_type)) - #cmd.append('design.set_property("{}","TX_EN_SER","0","{}")'.format(name, block_type)) + cmd.append('design.set_property("{}", "TX_SER", "{}", "{}")'.format(name, size, block_type)) cmd.append('design.set_property("{}", "TX_EN_SER", "{}", "{}")'.format(name, serdes, block_type)) cmd.append('design.set_property("{}", "TX_FASTCLK_PIN", "{}", "{}")'.format(name, fast_clk, block_type)) cmd.append('design.set_property("{}", "TX_MODE", "{}", "{}")'.format(name, tx_mode, block_type)) @@ -461,7 +469,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd.append('design.set_property("{}","RX_FIFO","0","{}")'.format(name, block_type)) cmd.append('design.set_property("{}","RX_HALF_RATE","{}","{}")'.format(name, half_rate, block_type)) cmd.append('design.set_property("{}","RX_ENA_PIN","{}","{}")'.format(name, ena, block_type)) - cmd.append('design.set_property("{}","RX_DESER","{}","{}")'.format(name, size, block_type)) cmd.append('design.set_property("{}","RX_DELAY_MODE","{}","{}")'.format(name, rx_delay, block_type)) cmd.append('design.set_property("{}","RX_DLY_ENA_PIN","{}","{}")'.format(name, delay_ena, block_type)) cmd.append('design.set_property("{}","RX_DLY_INC_PIN","{}","{}")'.format(name, delay_inc, block_type)) @@ -472,9 +479,11 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) #cmd.append('design.set_property("{}","RX_FIFO_RD_PIN","lvds_rx_inst1_RX_FIFO_RD","{}")'.format(name, block_type)) #cmd.append('design.set_property("{}","RX_LOCK_PIN","lvds_rx_inst1_RX_LOCK","{}")'.format(name, block_type)) else: - rx_delay = "0" if rx_delay == "STATIC" else "1" + rx_delay = "0" cmd.append('design.set_property("{}","RX_EN_DELAY","{}","{}")'.format(name, rx_delay, block_type)) + if not (self.platform.family == "Trion" and serdes == 0): + cmd.append('design.set_property("{}","RX_DESER","{}","{}")'.format(name, size, block_type)) cmd.append('design.set_property("{}","RX_CONN_TYPE","{}","{}")'.format(name, rx_mode, block_type)) cmd.append('design.set_property("{}","RX_DELAY","{}","{}")'.format(name, delay, block_type)) cmd.append('design.set_property("{}","RX_EN_DESER","{}","{}")'.format(name, serdes, block_type))