From 6f8a0052ef403669f20feabcc8c50a285657dfa9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Mon, 19 Jul 2021 13:36:48 +0200 Subject: [PATCH] soc/software/liblitedram: fix pattern checking for low DFI databits --- litex/soc/software/liblitedram/sdram.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 1e65d9601..3ced36b94 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -6,6 +6,7 @@ // This file is Copyright (c) 2018 Jean-François Nguyen // This file is Copyright (c) 2018 Sergiusz Bazanski // This file is Copyright (c) 2018 Tim 'mithro' Ansell +// This file is Copyright (c) 2021 Antmicro // License: BSD #include @@ -57,7 +58,7 @@ __attribute__((unused)) void cdelay(int i) #define MEMTEST_DATA_SIZE (2*1024*1024) #endif -#define DFII_PIX_DATA_BYTES SDRAM_PHY_DATABITS*SDRAM_PHY_XDR/8 +#define DFII_PIX_DATA_BYTES SDRAM_PHY_DFI_DATABITS/8 int sdram_get_databits(void) { return SDRAM_PHY_DATABITS; @@ -299,7 +300,7 @@ static void print_scan_errors(unsigned int errors) { #endif } -#define READ_CHECK_TEST_PATTERN_MAX_ERRORS (SDRAM_PHY_PHASES*2*32) +#define READ_CHECK_TEST_PATTERN_MAX_ERRORS (8*SDRAM_PHY_PHASES*SDRAM_PHY_XDR) static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int seed) { int p, i; @@ -346,8 +347,12 @@ static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int /* Read back test pattern */ csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr(p), tst, DFII_PIX_DATA_BYTES); /* Verify bytes matching current 'module' */ - errors += popcount(prs[p][ SDRAM_PHY_MODULES-1-module] ^ tst[ SDRAM_PHY_MODULES-1-module]); - errors += popcount(prs[p][2*SDRAM_PHY_MODULES-1-module] ^ tst[2*SDRAM_PHY_MODULES-1-module]); + for (int i = 0; i < DFII_PIX_DATA_BYTES; ++i) { + int j = p * DFII_PIX_DATA_BYTES + i; + if (j % SDRAM_PHY_MODULES == SDRAM_PHY_MODULES-1-module) { + errors += popcount(prs[p][i] ^ tst[i]); + } + } } #ifdef SDRAM_PHY_ECP5DDRPHY