From 181d41491104ad221850deb9e44d7c9a213f8c13 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Mar 2023 17:42:10 +0200 Subject: [PATCH] integration/soc/add_pcie: Expose more DMA parameters. --- litex/soc/integration/soc.py | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 0c027de62..9f493c974 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1959,9 +1959,12 @@ class LiteXSoC(SoC): # Add PCIe ------------------------------------------------------------------------------------- def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32, with_dma_buffering = True, dma_buffering_depth=1024, - with_dma_loopback = True, - with_msi = True, - with_synchronizer = False): + with_dma_loopback = True, + with_dma_synchronizer = False, + with_dma_monitor = False, + with_dma_status = False, + with_msi = True, +): # Imports from litepcie.core import LitePCIeEndpoint, LitePCIeMSI from litepcie.frontend.dma import LitePCIeDMA @@ -2000,7 +2003,9 @@ class LiteXSoC(SoC): dma = LitePCIeDMA(phy, endpoint, with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth, with_loopback = with_dma_loopback, - with_synchronizer = with_synchronizer, + with_synchronizer = with_dma_synchronizer, + with_monitor = with_dma_monitor, + with_status = with_dma_status, address_width = address_width ) setattr(self, f"{name}_dma{i}", dma)