From 18c0541e6aae0781c4897ecb55ac64ae4d86a620 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 3 Nov 2023 11:53:32 +0100
Subject: [PATCH] gen/fhdl/instance: Add instance description.

---
 litex/gen/fhdl/instance.py | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/litex/gen/fhdl/instance.py b/litex/gen/fhdl/instance.py
index ba08e4562..47f1913b1 100644
--- a/litex/gen/fhdl/instance.py
+++ b/litex/gen/fhdl/instance.py
@@ -11,7 +11,17 @@ from migen.fhdl.specials  import *
 # LiteX Instance Verilog Generation ----------------------------------------------------------------
 
 def _instance_generate_verilog(instance, ns, add_data_file):
-    r = instance.of + " "
+    r = ""
+
+    # Instance Description.
+    # ---------------------
+    r += "//" + "-"*78 + "\n"
+    r += f"// Instance {ns.get_name(instance)} of {instance.of} Module.\n"
+    r += "//" + "-"*78 + "\n"
+
+    # Instance Name.
+    # --------------
+    r += instance.of + " "
 
     # Instance Parameters.
     # --------------------
@@ -23,7 +33,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
             if not first:
                 r += ",\n"
             first = False
-            r += "\t." + p.name + "("
+            r += f"\t.{p.name}("
             # Constant.
             if isinstance(p.value, Constant):
                 r += verilog_printexpr(ns, p.value)[0]
@@ -35,7 +45,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
                 r += p.value
             # String.
             elif isinstance(p.value, str):
-                r += "\"" + p.value + "\""
+                r += f"\"{p.value}\""
             else:
                 raise TypeError
             r += ")"