diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 1fdbfd5ed..e074c47ee 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT41K128M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy.mii import LiteEthPHYMII
 from liteeth.core.mac import LiteEthMAC
@@ -107,7 +107,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         self.add_constant("READ_LEVELING_BITSLIP", 3)
         self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K128M16(self.clk_freq, "1:4")
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 86ebe291a..89498d675 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT8JTF12864
-from litedram.phy import k7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy import LiteEthPHY
 from liteeth.core.mac import LiteEthMAC
@@ -89,7 +89,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
         sdram_module = MT8JTF12864(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index ee13a6ef3..fd33159c5 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT47H64M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 
 class _CRG(Module):
@@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         sdram_module = MT47H64M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index b0265187d..70e054ec1 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT41K256M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 from liteeth.core.mac import LiteEthMAC
@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         self.add_constant("READ_LEVELING_BITSLIP", 3)
         self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K256M16(self.clk_freq, "1:4")