From 1925ba176fa7c37050c5b8e17b7fd2bd26462a18 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 23 Feb 2018 13:38:19 +0100 Subject: [PATCH] replace litex.gen imports with migen imports --- litex/boards/targets/arty.py | 4 ++-- litex/boards/targets/de0nano.py | 3 ++- litex/boards/targets/kc705.py | 4 ++-- litex/boards/targets/minispartan6.py | 5 +++-- litex/boards/targets/nexys4ddr.py | 4 ++-- litex/boards/targets/nexys_video.py | 4 ++-- litex/boards/targets/sim.py | 5 +++-- litex/boards/targets/simple.py | 4 ++-- litex/build/altera/common.py | 6 +++--- litex/build/altera/quartus.py | 2 +- litex/build/generic_platform.py | 9 +++++---- litex/build/lattice/common.py | 8 ++++---- litex/build/lattice/diamond.py | 4 ++-- litex/build/lattice/icestorm.py | 2 +- litex/build/sim/platform.py | 5 +++-- litex/build/sim/verilator.py | 3 ++- litex/build/xilinx/common.py | 12 ++++++------ litex/build/xilinx/ise.py | 3 ++- litex/build/xilinx/vivado.py | 3 ++- litex/gen/__init__.py | 10 ---------- litex/gen/fhdl/verilog.py | 10 +++++----- litex/gen/sim/__init__.py | 2 +- litex/gen/sim/core.py | 18 +++++++++--------- litex/gen/sim/vcd.py | 2 +- litex/soc/cores/code_8b10b.py | 2 +- litex/soc/cores/cordic.py | 2 +- litex/soc/cores/cpu/lm32/core.py | 2 +- litex/soc/cores/cpu/mor1kx/core.py | 2 +- litex/soc/cores/cpu/picorv32/core.py | 2 +- litex/soc/cores/dna.py | 3 ++- litex/soc/cores/frequency_meter.py | 6 +++--- litex/soc/cores/gpio.py | 4 ++-- litex/soc/cores/identifier.py | 2 +- litex/soc/cores/nor_flash_16.py | 4 ++-- litex/soc/cores/spi.py | 3 ++- litex/soc/cores/spi_flash.py | 4 ++-- litex/soc/cores/timer.py | 2 +- litex/soc/cores/uart.py | 6 +++--- litex/soc/cores/xadc.py | 3 ++- litex/soc/integration/cpu_interface.py | 2 +- litex/soc/integration/sdram_init.py | 2 +- litex/soc/integration/soc_core.py | 2 +- litex/soc/integration/soc_sdram.py | 6 +++--- litex/soc/interconnect/axi.py | 7 ++++--- litex/soc/interconnect/csr.py | 6 +++--- litex/soc/interconnect/csr_bus.py | 8 ++++---- litex/soc/interconnect/csr_eventmanager.py | 4 ++-- litex/soc/interconnect/stream.py | 18 +++++++++--------- litex/soc/interconnect/stream_packet.py | 8 ++++---- litex/soc/interconnect/stream_sim.py | 3 ++- litex/soc/interconnect/wishbone.py | 10 +++++----- litex/soc/interconnect/wishbone2csr.py | 4 ++-- litex/soc/interconnect/wishbonebridge.py | 8 ++++---- test/test_bitslip.py | 4 ++-- test/test_code_8b10b.py | 2 +- test/test_gearbox.py | 4 ++-- test/test_targets.py | 2 +- 57 files changed, 141 insertions(+), 138 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index c3e5dd70e..1fdbfd5ed 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -2,8 +2,8 @@ import argparse -from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import arty diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 17da0e725..813241a96 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -2,7 +2,8 @@ import argparse -from litex.gen import * +from migen import * + from litex.boards.platforms import de0nano from litex.soc.integration.soc_sdram import * diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 541d3dea9..86ebe291a 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -2,8 +2,8 @@ import argparse -from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import kc705 diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 7c6223671..6cff5bee3 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -3,8 +3,9 @@ import argparse from fractions import Fraction -from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + from litex.boards.platforms import minispartan6 from litex.soc.integration.soc_sdram import * diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index c0ece9e1d..ee13a6ef3 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -2,8 +2,8 @@ import argparse -from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import nexys4ddr diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index daa9c9803..b0265187d 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -2,8 +2,8 @@ import argparse -from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import nexys_video diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index a10479d2f..1cd08bd67 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -3,9 +3,10 @@ import argparse import importlib -from litex.gen import * +from migen import * +from migen.genlib.io import CRG + from litex.boards.platforms import sim -from litex.gen.genlib.io import CRG from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 88c8afd37..ccc8cbc3c 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -3,8 +3,8 @@ import argparse import importlib -from litex.gen import * -from litex.gen.genlib.io import CRG +from migen import * +from migen.genlib.io import CRG from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py index 07b6ef76a..fafb49837 100644 --- a/litex/build/altera/common.py +++ b/litex/build/altera/common.py @@ -1,6 +1,6 @@ -from litex.gen.fhdl.module import Module -from litex.gen.fhdl.specials import Instance -from litex.gen.genlib.io import DifferentialInput, DifferentialOutput +from migen.fhdl.module import Module +from migen.fhdl.specials import Instance +from migen.genlib.io import DifferentialInput, DifferentialOutput class AlteraDifferentialInputImpl(Module): diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py index af34b2eb4..4dae8edf3 100644 --- a/litex/build/altera/quartus.py +++ b/litex/build/altera/quartus.py @@ -4,7 +4,7 @@ import os import subprocess -from litex.gen.fhdl.structure import _Fragment +from migen.fhdl.structure import _Fragment from litex.build.generic_platform import Pins, IOStandard, Misc from litex.build import tools diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py index 1ab5935e5..83c0825a7 100644 --- a/litex/build/generic_platform.py +++ b/litex/build/generic_platform.py @@ -1,9 +1,10 @@ import os -from litex.gen.fhdl.structure import Signal -from litex.gen.genlib.record import Record -from litex.gen.genlib.io import CRG -from litex.gen.fhdl import verilog +from migen.fhdl.structure import Signal +from migen.genlib.record import Record +from migen.genlib.io import CRG +from migen.fhdl import verilog + from litex.build import tools diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py index 0050e4147..b6d8ec1af 100644 --- a/litex/build/lattice/common.py +++ b/litex/build/lattice/common.py @@ -1,7 +1,7 @@ -from litex.gen.fhdl.module import Module -from litex.gen.fhdl.specials import Instance -from litex.gen.genlib.io import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from migen.fhdl.module import Module +from migen.fhdl.specials import Instance +from migen.genlib.io import * +from migen.genlib.resetsync import AsyncResetSynchronizer class DiamondAsyncResetSynchronizerImpl(Module): diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py index bfc72fbbe..d0594ec9e 100644 --- a/litex/build/lattice/diamond.py +++ b/litex/build/lattice/diamond.py @@ -6,8 +6,8 @@ import sys import subprocess import shutil -from litex.gen.fhdl.structure import _Fragment -from litex.gen.fhdl.verilog import DummyAttrTranslate +from migen.fhdl.structure import _Fragment +from migen.fhdl.verilog import DummyAttrTranslate from litex.build.generic_platform import * from litex.build import tools diff --git a/litex/build/lattice/icestorm.py b/litex/build/lattice/icestorm.py index 985101026..5fd21ff23 100644 --- a/litex/build/lattice/icestorm.py +++ b/litex/build/lattice/icestorm.py @@ -5,7 +5,7 @@ import os import sys import subprocess -from litex.gen.fhdl.structure import _Fragment +from migen.fhdl.structure import _Fragment from litex.build.generic_platform import * from litex.build import tools diff --git a/litex/build/sim/platform.py b/litex/build/sim/platform.py index f76532a4c..19ab63ebf 100644 --- a/litex/build/sim/platform.py +++ b/litex/build/sim/platform.py @@ -1,5 +1,6 @@ -from litex.gen.fhdl.structure import Signal -from litex.gen.genlib.record import Record +from migen.fhdl.structure import Signal +from migen.genlib.record import Record + from litex.build.generic_platform import GenericPlatform from litex.build.sim import common, verilator diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index a2e39b47a..72b7d5e99 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -5,7 +5,8 @@ import os import subprocess -from litex.gen.fhdl.structure import _Fragment +from migen.fhdl.structure import _Fragment + from litex.build import tools from litex.build.generic_platform import * diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index 4c59a9983..57ae89310 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -11,12 +11,12 @@ try: except ImportError: _have_colorama = False -from litex.gen.fhdl.structure import * -from litex.gen.fhdl.specials import Instance -from litex.gen.fhdl.module import Module -from litex.gen.genlib.cdc import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen.genlib.io import * +from migen.fhdl.structure import * +from migen.fhdl.specials import Instance +from migen.fhdl.module import Module +from migen.genlib.cdc import * +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.genlib.io import * from litex.build import tools diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index 171fbef0c..2d51e6950 100644 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -2,7 +2,8 @@ import os import subprocess import sys -from litex.gen.fhdl.structure import _Fragment +from migen.fhdl.structure import _Fragment + from litex.build.generic_platform import * from litex.build import tools from litex.build.xilinx import common diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index ea5eb0111..5201dc5f6 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -5,7 +5,8 @@ import os import subprocess import sys -from litex.gen.fhdl.structure import _Fragment +from migen.fhdl.structure import _Fragment + from litex.build.generic_platform import * from litex.build import tools from litex.build.xilinx import common diff --git a/litex/gen/__init__.py b/litex/gen/__init__.py index 2cd382534..7d751ff9b 100644 --- a/litex/gen/__init__.py +++ b/litex/gen/__init__.py @@ -1,11 +1 @@ -from litex.gen.fhdl.structure import * -from litex.gen.fhdl.module import * -from litex.gen.fhdl.specials import * -from litex.gen.fhdl.bitcontainer import * -from litex.gen.fhdl.decorators import * -from litex.gen.fhdl.simplify import * - from litex.gen.sim import * - -from litex.gen.genlib.record import * -from litex.gen.genlib.fsm import * diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 8ce67bc0e..9ed17b0e7 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -2,11 +2,11 @@ from functools import partial from operator import itemgetter import collections -from litex.gen.fhdl.structure import * -from litex.gen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment -from litex.gen.fhdl.tools import * -from litex.gen.fhdl.namer import build_namespace -from litex.gen.fhdl.conv_output import ConvOutput +from migen.fhdl.structure import * +from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment +from migen.fhdl.tools import * +from migen.fhdl.namer import build_namespace +from migen.fhdl.conv_output import ConvOutput _reserved_keywords = { diff --git a/litex/gen/sim/__init__.py b/litex/gen/sim/__init__.py index 853486a66..e04060e16 100644 --- a/litex/gen/sim/__init__.py +++ b/litex/gen/sim/__init__.py @@ -1 +1 @@ -from litex.gen.sim.core import Simulator, run_simulation, passive +from migen.sim.core import Simulator, run_simulation, passive diff --git a/litex/gen/sim/core.py b/litex/gen/sim/core.py index 2ab9b4bd3..e3db45f6f 100644 --- a/litex/gen/sim/core.py +++ b/litex/gen/sim/core.py @@ -3,18 +3,18 @@ import collections import inspect from functools import wraps -from litex.gen.fhdl.structure import * -from litex.gen.fhdl.structure import (_Value, _Statement, +from migen.fhdl.structure import * +from migen.fhdl.structure import (_Value, _Statement, _Operator, _Slice, _ArrayProxy, _Assign, _Fragment) -from litex.gen.fhdl.bitcontainer import value_bits_sign -from litex.gen.fhdl.tools import (list_targets, list_signals, +from migen.fhdl.bitcontainer import value_bits_sign +from migen.fhdl.tools import (list_targets, list_signals, insert_resets, lower_specials) -from litex.gen.fhdl.simplify import MemoryToArray -from litex.gen.fhdl.specials import _MemoryLocation -from litex.gen.fhdl.module import Module -from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter +from migen.fhdl.simplify import MemoryToArray +from migen.fhdl.specials import _MemoryLocation +from migen.fhdl.module import Module +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.sim.vcd import VCDWriter, DummyVCDWriter class ClockState: diff --git a/litex/gen/sim/vcd.py b/litex/gen/sim/vcd.py index db369a6dc..25441b14e 100644 --- a/litex/gen/sim/vcd.py +++ b/litex/gen/sim/vcd.py @@ -4,7 +4,7 @@ import os from collections import OrderedDict import shutil -from litex.gen.fhdl.namer import build_namespace +from migen.fhdl.namer import build_namespace def vcd_codes(): diff --git a/litex/soc/cores/code_8b10b.py b/litex/soc/cores/code_8b10b.py index 16d167c91..2e9428535 100644 --- a/litex/soc/cores/code_8b10b.py +++ b/litex/soc/cores/code_8b10b.py @@ -12,7 +12,7 @@ Note: This encoding is *not* used by DVI/HDMI (that uses a *different* 8b/10b scheme called TMDS). """ -from litex.gen import * +from migen import * def disparity(word, nbits): diff --git a/litex/soc/cores/cordic.py b/litex/soc/cores/cordic.py index c5db7e1df..14a928532 100644 --- a/litex/soc/cores/cordic.py +++ b/litex/soc/cores/cordic.py @@ -17,7 +17,7 @@ from math import atan, atanh, log, sqrt, pi -from litex.gen import * +from migen import * class TwoQuadrantCordic(Module): diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 743a61f63..03d99efcc 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -1,6 +1,6 @@ import os -from litex.gen import * +from migen import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 872300595..f607d044d 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -1,6 +1,6 @@ import os -from litex.gen import * +from migen import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 9a0af3a37..dbce1c641 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -1,6 +1,6 @@ import os -from litex.gen import * +from migen import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/dna.py b/litex/soc/cores/dna.py index 324659d7e..8e8ea6410 100644 --- a/litex/soc/cores/dna.py +++ b/litex/soc/cores/dna.py @@ -1,6 +1,7 @@ # Copyright 2014-2015 Robert Jordens -from litex.gen import * +from migen import * + from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/frequency_meter.py b/litex/soc/cores/frequency_meter.py index 8b35c514d..3e6159ee2 100644 --- a/litex/soc/cores/frequency_meter.py +++ b/litex/soc/cores/frequency_meter.py @@ -1,6 +1,6 @@ -from litex.gen import * -from litex.gen.genlib.cdc import MultiReg, GrayCounter -from litex.gen.genlib.cdc import GrayDecoder +from migen import * +from migen.genlib.cdc import MultiReg, GrayCounter +from migen.genlib.cdc import GrayDecoder from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 463e1e20c..89ccd54d3 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -1,5 +1,5 @@ -from litex.gen import * -from litex.gen.genlib.cdc import MultiReg +from migen import * +from migen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/identifier.py b/litex/soc/cores/identifier.py index 07fc08efd..377600fd9 100644 --- a/litex/soc/cores/identifier.py +++ b/litex/soc/cores/identifier.py @@ -1,4 +1,4 @@ -from litex.gen import * +from migen import * class Identifier(Module): diff --git a/litex/soc/cores/nor_flash_16.py b/litex/soc/cores/nor_flash_16.py index 3027882a0..fa6e0c087 100644 --- a/litex/soc/cores/nor_flash_16.py +++ b/litex/soc/cores/nor_flash_16.py @@ -1,5 +1,5 @@ -from litex.gen import * -from litex.gen.genlib.fsm import FSM, NextState +from migen import * +from migen.genlib.fsm import FSM, NextState from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py index bda81f044..caa470dd2 100644 --- a/litex/soc/cores/spi.py +++ b/litex/soc/cores/spi.py @@ -1,6 +1,7 @@ from itertools import product -from litex.gen import * +from migen import * + from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index 14df3a4db..4447e9f91 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -1,5 +1,5 @@ -from litex.gen import * -from litex.gen.genlib.misc import timeline +from migen import * +from migen.genlib.misc import timeline from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus diff --git a/litex/soc/cores/timer.py b/litex/soc/cores/timer.py index d98a85e95..fdfefde2d 100644 --- a/litex/soc/cores/timer.py +++ b/litex/soc/cores/timer.py @@ -1,4 +1,4 @@ -from litex.gen import * +from migen import * from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index a32b6e5b9..0b7d5b53a 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -1,6 +1,6 @@ -from litex.gen import * -from litex.gen.genlib.record import Record -from litex.gen.genlib.cdc import MultiReg +from migen import * +from migen.genlib.record import Record +from migen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * diff --git a/litex/soc/cores/xadc.py b/litex/soc/cores/xadc.py index e990a29ea..1b044d6f3 100644 --- a/litex/soc/cores/xadc.py +++ b/litex/soc/cores/xadc.py @@ -1,6 +1,7 @@ # Copyright 2014-2015 Robert Jordens -from litex.gen import * +from migen import * + from litex.soc.interconnect.csr import * diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py index fd1e4afb9..185d674ce 100644 --- a/litex/soc/integration/cpu_interface.py +++ b/litex/soc/integration/cpu_interface.py @@ -1,6 +1,6 @@ import os -from litex.gen import * +from migen import * from litex.soc.interconnect.csr import CSRStatus diff --git a/litex/soc/integration/sdram_init.py b/litex/soc/integration/sdram_init.py index 1f73c1ecb..8ca1db005 100644 --- a/litex/soc/integration/sdram_init.py +++ b/litex/soc/integration/sdram_init.py @@ -1,4 +1,4 @@ -from litex.gen import log2_int +from migen import log2_int def get_sdram_phy_header(sdram_phy_settings): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 02fe0c9c8..7f6dd75ae 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -1,6 +1,6 @@ from operator import itemgetter -from litex.gen import * +from migen import * from litex.soc.cores import identifier, timer, uart from litex.soc.cores.cpu import lm32, mor1kx, picorv32 diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 4969bd598..1c9064c21 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -1,5 +1,5 @@ -from litex.gen import * -from litex.gen.genlib.record import * +from migen import * +from migen.genlib.record import * from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import AutoCSR @@ -79,7 +79,7 @@ class SoCSDRAM(SoCCore): # Remove this workaround when fixed by Xilinx. from litex.build.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): - from litex.gen.fhdl.simplify import FullMemoryWE + from migen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: self.submodules.l2_cache = l2_cache diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 3d3570b7d..27c45fde2 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -6,8 +6,9 @@ import math -from litex.gen import * -from litex.gen.genlib.record import * +from migen import * +from migen.genlib.record import * + from litex.soc.interconnect import csr_bus # Layout of AXI4 Lite Bus @@ -179,7 +180,7 @@ class AXILite2CSR(Module): ) -from litex.gen.sim import run_simulation +from migen.sim import run_simulation from litex.soc.interconnect import csr, csr_bus def test_axilite2csr(): diff --git a/litex/soc/interconnect/csr.py b/litex/soc/interconnect/csr.py index b34802fcd..941533695 100644 --- a/litex/soc/interconnect/csr.py +++ b/litex/soc/interconnect/csr.py @@ -24,9 +24,9 @@ class, which provides ``get_csrs`` and ``get_memories`` methods that scan for CSR and memory attributes and return their list. """ -from litex.gen import * -from litex.gen.util.misc import xdir -from litex.gen.fhdl.tracer import get_obj_var_name +from migen import * +from migen.util.misc import xdir +from migen.fhdl.tracer import get_obj_var_name class _CSRBase(DUID): diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index 86a9dad45..74a84b448 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -6,10 +6,10 @@ The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing the configuration and status registers of cores from software. """ -from litex.gen import * -from litex.gen.genlib.record import * -from litex.gen.genlib.misc import chooser -from litex.gen.util.misc import xdir +from migen import * +from migen.genlib.record import * +from migen.genlib.misc import chooser +from migen.util.misc import xdir from litex.soc.interconnect import csr from litex.soc.interconnect.csr import CSRStorage diff --git a/litex/soc/interconnect/csr_eventmanager.py b/litex/soc/interconnect/csr_eventmanager.py index 07a32c336..9ec31229c 100644 --- a/litex/soc/interconnect/csr_eventmanager.py +++ b/litex/soc/interconnect/csr_eventmanager.py @@ -6,8 +6,8 @@ controllers. from functools import reduce from operator import or_ -from litex.gen import * -from litex.gen.util.misc import xdir +from migen import * +from migen.util.misc import xdir from litex.soc.interconnect.csr import * diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index fea05b43e..5a070ea7e 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -1,16 +1,16 @@ -from litex.gen import * -from litex.gen.genlib.record import * -from litex.gen.genlib import fifo +from migen import * +from migen.genlib.record import * +from migen.genlib import fifo (DIR_SINK, DIR_SOURCE) = range(2) -def _make_m2s(layout, reset_less=False): +def _make_m2s(layout): r = [] for f in layout: if isinstance(f[1], (int, tuple)): - r.append((f[0], f[1], DIR_M_TO_S, reset_less)) + r.append((f[0], f[1], DIR_M_TO_S)) else: - r.append((f[0], _make_m2s(f[1], reset_less))) + r.append((f[0], _make_m2s(f[1]))) return r @@ -34,8 +34,8 @@ class EndpointDescription: ("ready", 1, DIR_S_TO_M), ("first", 1, DIR_M_TO_S), ("last", 1, DIR_M_TO_S), - ("payload", _make_m2s(self.payload_layout, True)), - ("param", _make_m2s(self.param_layout, True)) + ("payload", _make_m2s(self.payload_layout)), + ("param", _make_m2s(self.param_layout)) ] return full_layout @@ -359,7 +359,7 @@ class StrideConverter(Module): # XXX from copy import copy -from litex.gen.util.misc import xdir +from migen.util.misc import xdir def _rawbits_layout(l): if isinstance(l, int): diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index 8e4dff15e..cd178e0bd 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -1,7 +1,7 @@ -from litex.gen import * -from litex.gen.genlib.roundrobin import * -from litex.gen.genlib.record import * -from litex.gen.genlib.fsm import FSM, NextState +from migen import * +from migen.genlib.roundrobin import * +from migen.genlib.record import * +from migen.genlib.fsm import FSM, NextState from litex.soc.interconnect import stream diff --git a/litex/soc/interconnect/stream_sim.py b/litex/soc/interconnect/stream_sim.py index 7b6863078..eacb5c5b1 100644 --- a/litex/soc/interconnect/stream_sim.py +++ b/litex/soc/interconnect/stream_sim.py @@ -2,7 +2,8 @@ import random import math from copy import deepcopy -from litex.gen import * +from migen import * + from litex.soc.interconnect import stream # TODO: clean up code below diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 2f2798c7b..8f3437c12 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -1,11 +1,11 @@ from functools import reduce from operator import or_ -from litex.gen import * -from litex.gen.genlib import roundrobin -from litex.gen.genlib.record import * -from litex.gen.genlib.misc import split, displacer, chooser -from litex.gen.genlib.fsm import FSM, NextState +from migen import * +from migen.genlib import roundrobin +from migen.genlib.record import * +from migen.genlib.misc import split, displacer, chooser +from migen.genlib.fsm import FSM, NextState from litex.soc.interconnect import csr diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py index 25efdc6fd..1d7171a31 100644 --- a/litex/soc/interconnect/wishbone2csr.py +++ b/litex/soc/interconnect/wishbone2csr.py @@ -1,5 +1,5 @@ -from litex.gen import * -from litex.gen.genlib.misc import timeline +from migen import * +from migen.genlib.misc import timeline from litex.soc.interconnect import csr_bus, wishbone diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py index b9f9d1095..06feeffdd 100644 --- a/litex/soc/interconnect/wishbonebridge.py +++ b/litex/soc/interconnect/wishbonebridge.py @@ -1,8 +1,8 @@ -from litex.gen import * +from migen import * -from litex.gen.genlib.misc import chooser, WaitTimer -from litex.gen.genlib.record import Record -from litex.gen.genlib.fsm import FSM, NextState +from migen.genlib.misc import chooser, WaitTimer +from migen.genlib.record import Record +from migen.genlib.fsm import FSM, NextState from litex.soc.interconnect import wishbone from litex.soc.interconnect import stream diff --git a/test/test_bitslip.py b/test/test_bitslip.py index 8927f0c04..ef8011575 100644 --- a/test/test_bitslip.py +++ b/test/test_bitslip.py @@ -1,8 +1,8 @@ import unittest import random -from litex.gen import * -from litex.gen.genlib.misc import BitSlip +from migen import * +from migen.genlib.misc import BitSlip class BitSlipModel: diff --git a/test/test_code_8b10b.py b/test/test_code_8b10b.py index 56d847150..38ad433f5 100644 --- a/test/test_code_8b10b.py +++ b/test/test_code_8b10b.py @@ -2,7 +2,7 @@ import unittest import random from collections import namedtuple -from litex.gen import * +from migen import * from litex.soc.cores import code_8b10b diff --git a/test/test_gearbox.py b/test/test_gearbox.py index c8ecfad61..9ec2ad2d6 100644 --- a/test/test_gearbox.py +++ b/test/test_gearbox.py @@ -1,8 +1,8 @@ import unittest import random -from litex.gen import * -from litex.gen.genlib.cdc import Gearbox +from migen import * +from migen.genlib.cdc import Gearbox # TODO: # connect two gearbox together: diff --git a/test/test_targets.py b/test/test_targets.py index 89c1b28e5..591353ece 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -1,7 +1,7 @@ import unittest import os -from litex.gen import * +from migen import * from litex.soc.integration.builder import *