From 1938ce363d21b6a21678ab4dfa9f84eb622417a6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Jul 2020 11:10:05 +0200 Subject: [PATCH] integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports. --- litex/soc/integration/soc.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 838e65b3d..40ae46a51 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1157,6 +1157,13 @@ class LiteXSoC(SoC): # Add SDRAM region self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) + # Add CPU's direct memory buses (if not already declared) ---------------------------------- + if hasattr(self.cpu, "add_memory_buses"): + self.cpu.add_memory_buses( + address_width = 32, + data_width = self.sdram.crossbar.controller.data_width + ) + # SoC [<--> L2 Cache] <--> LiteDRAM -------------------------------------------------------- if len(self.cpu.memory_buses): # When CPU has at least a direct memory bus, connect them directly to LiteDRAM.