From 195cc915ed3cc6460838c2e484b836ac1e710e03 Mon Sep 17 00:00:00 2001 From: Thomas Watson Date: Fri, 5 Aug 2022 02:20:03 +0000 Subject: [PATCH] cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus --- litex/soc/cores/cpu/vexriscv_smp/core.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index e0c446211..e2ec162be 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -369,6 +369,10 @@ class VexRiscvSMP(CPU): from litex.build.altera import AlteraPlatform if isinstance(platform, AlteraPlatform): ram_filename = "Ram_1w_1rs_Intel.v" + # define SYNTHESIS verilog name to avoid issues with unsupported + # functions + platform.toolchain.additional_qsf_commands.append( + 'set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"') # On Efinix platforms, use specific implementation. from litex.build.efinix import EfinixPlatform if isinstance(platform, EfinixPlatform):