diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py
index f74171511..206e7f358 100644
--- a/litex/soc/interconnect/axi/axi_full.py
+++ b/litex/soc/interconnect/axi/axi_full.py
@@ -143,6 +143,7 @@ class AXIInterface:
 # AXI Remapper -------------------------------------------------------------------------------------
 
 class AXIRemapper(LiteXModule):
+    """Remaps AXI addresses by applying an origin offset and address mask."""
     def __init__(self, master, slave, origin, size):
         # Mask.
         mask = 2**int(log2(size)) - 1
diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py
index 1289d63c3..ed7909336 100644
--- a/litex/soc/interconnect/axi/axi_lite.py
+++ b/litex/soc/interconnect/axi/axi_lite.py
@@ -134,6 +134,7 @@ class AXILiteInterface:
 # AXI-Lite Remapper --------------------------------------------------------------------------------
 
 class AXILiteRemapper(LiteXModule):
+    """Remaps AXI Lite addresses by applying an origin offset and address mask."""
     def __init__(self, master, slave, origin, size):
         # Mask.
         mask = 2**int(log2(size)) - 1
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 2f7665468..6a7ffe22e 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -129,6 +129,7 @@ class Interface(Record):
 # Wishbone Remapper --------------------------------------------------------------------------------
 
 class Remapper(LiteXModule):
+    """Remaps Wishbone addresses by applying an origin offset and address mask."""
     def __init__(self, master, slave, origin, size):
         # Parameters.
         addressing = master.addressing