diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index 43fa14e5c..e6d0f43b1 100644
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -13,7 +13,7 @@ class Bank:
 		comb = []
 		sync = []
 		
-		comb.append(self._sel.eq(self.interface.a_i[10:] == Constant(self.address, BV(4))))
+		comb.append(self._sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5))))
 		
 		nregs = len(self.description)
 		nbits = bits_for(nregs-1)
@@ -53,10 +53,10 @@ class Bank:
 				else:
 					brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
 		if brcases:
-			sync.append(self.interface.d_o.eq(Constant(0, BV(32))))
+			sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
 			sync.append(If(self._sel, Case(self.interface.a_i[:nbits], *brcases)))
 		else:
-			comb.append(self.interface.d_o.eq(Constant(0, BV(32))))
+			comb.append(self.interface.d_o.eq(Constant(0, BV(8))))
 		
 		# Device access
 		for reg in self.description:
diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index b5f40a614..8e5af9a60 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -4,8 +4,8 @@ from migen.bus.simple import Simple
 _desc = [
 	(True,	"a",	14),
 	(True,	"we",	1),
-	(True,	"d",	32),
-	(False,	"d",	32)
+	(True,	"d",	8),
+	(False,	"d",	8)
 ]
 
 class Master(Simple):
@@ -23,7 +23,7 @@ class Interconnect:
 	
 	def get_fragment(self):
 		comb = []
-		rb = Constant(0, BV(32))
+		rb = Constant(0, BV(8))
 		for slave in self.slaves:
 			comb.append(slave.a_i.eq(self.master.a_o))
 			comb.append(slave.we_i.eq(self.master.we_o))