From 1b32d8a34160a40a6d93e5a6b0e3c9a9eb168878 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 9 Feb 2024 15:10:47 +0100
Subject: [PATCH] soc/add_etherbone: Revert sys_clk domain renaming when ethmac
 is disabled.

---
 litex/soc/integration/soc.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 121d3b691..2aab9e24f 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1844,7 +1844,9 @@ class LiteXSoC(SoC):
             # Use PHY's eth_tx/eth_rx clock domains.
             ethcore = ClockDomainsRenamer({
                 "eth_tx": phy_cd + "_tx",
-                "eth_rx": phy_cd + "_rx"})(ethcore)
+                "eth_rx": phy_cd + "_rx",
+                "sys"   : {True: "sys", False: phy_cd + "_rx"}[with_ethmac],
+            })(ethcore)
         self.add_module(name=f"ethcore_{name}", module=ethcore)
 
         etherbone_cd = "sys"