From f687425cb1958d549de54480adec264eedee4901 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 18 Jul 2024 11:26:13 +0200 Subject: [PATCH] Update VexiiRiscv --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index c15c2dc83..4d79bf2e9 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -148,7 +148,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ee92608a", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "7b16ef32", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard"