From 1c4d64f46b40ccfbfed8b2314b2b4371340d5e20 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 1 Sep 2022 11:22:25 +0200 Subject: [PATCH] CHANGES: Update. --- CHANGES | 95 ++++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 63 insertions(+), 32 deletions(-) diff --git a/CHANGES b/CHANGES index 2e72fb988..099b95722 100644 --- a/CHANGES +++ b/CHANGES @@ -6,46 +6,77 @@ - cpu/vexriscv: Fix compilation with new binutils. - soc/LiteXSocArgumentParser: Fix --cpu-type parsing. - litex_sim: Fix --with-ethernet. + - liblitesdcard: Fix SDCard initialization corner cases. + - liblitedram: Enable sdram_init/mr_write for SDRAM. + - export/get_memory_x: Replace SPIFlash with ROM. + - soc/cores/video: Fix operation with some monitors (set data to 0 during blanking). + - tools/remote/comm_usb: Fix multi-word reads/writes. + - build/lattice/oxide: Fix ES posfix on device name. + - interconnect/axi: Fix AXIArbiter corner case. + - litex_server/client: Fix remapping over CommPCIe. + - LitePCIe: Fix LiteUART support with multi-boards. - [> Added Features + [> Added Features ----------------- - - litex_setup: Add -tag support for install/update. - - tools: Add initial LiteX standalone SoC generator. - - cores/ram: Add Xilinx's FIFO_SYNC_MACRO equivalent. - - LitePCIe: Always use 24-bit depth fields on LitePCIeBuffering to simplify software. - - gen/fhdl: Integrate Migen namer to give us more flexibility. - - fhdl/memory: Prefix memory files with build name to simplify reuse/integration. - - cpu/rocket: Add more variants. - - cores/video: Enable driving both + and - diff outs to compensate hardware issues. - - build: Add intial OSFPGA Foedag/Raptor build backend. - - cpu/cva5: Add initial CVA5 CPU support (ex Taiga). - - LiteSATA: Add IRQ and Identify support. - - clock/intel: Improve to find the best PLL config. - - cpu/cva6: Add initial CVA6 CPU support (ex Ariane). - - bios: Improve config flags. - - tools: Add I2s/MMCM support to litex_json2dts_zephyr. - - clock/gowin: Add GW2A support. - - bios: Disable LTO (does not work in all cases, needs to be investigated). - - CI: Test more RISC-V CPUs and OpenRisc CPUs in CI. - - bios: Add CONFIG_NO_BOOT to allow disabling boot sequence. - - export: Allow disabling CSR_BASE define in csr.h. - - build/openocd: Update for compatibility with upstream OpenOCD. - - cpu/openc906: Add initial OpenC906 support (open version of the Allwinner's D1 chip). - - soc: Add automatic bridging between AXI <-> AXI-Lite <-> Wishbone. - - soc: Add AXI-Full bus support. - - interconnect: Add AXI DownConverted and Interconnect/Crossbar. - - interconnect: Create axi directory and split code. - - soc: Modify SoC finalization order for more flexibility. - - soc: Add --bus-interconnect parameter to select interconect: shared/crossbar. - - valentyusb: Package and install it with LiteX. - - bios/mem_list: Align Mem Regions. + - litex_setup: Add -tag support for install/update. + - tools: Add initial LiteX standalone SoC generator. + - cores/ram: Add Xilinx's FIFO_SYNC_MACRO equivalent. + - LitePCIe: Always use 24-bit depth fields on LitePCIeBuffering to simplify software. + - gen/fhdl: Integrate Migen namer to give us more flexibility. + - fhdl/memory: Prefix memory files with build name to simplify reuse/integration. + - cpu/rocket: Add more variants. + - cores/video: Enable driving both + and - diff outs to compensate hardware issues. + - build: Add intial OSFPGA Foedag/Raptor build backend. + - cpu/cva5: Add initial CVA5 CPU support (ex Taiga). + - LiteSATA: Add IRQ and Identify support. + - clock/intel: Improve to find the best PLL config. + - cpu/cva6: Add initial CVA6 CPU support (ex Ariane). + - bios: Improve config flags. + - tools: Add I2s/MMCM support to litex_json2dts_zephyr. + - clock/gowin: Add GW2A support. + - bios: Disable LTO (does not work in all cases, needs to be investigated). + - CI: Test more RISC-V CPUs and OpenRisc CPUs in CI. + - bios: Add CONFIG_NO_BOOT to allow disabling boot sequence. + - export: Allow disabling CSR_BASE define in csr.h. + - build/openocd: Update for compatibility with upstream OpenOCD. + - cpu/openc906: Add initial OpenC906 support (open version of the Allwinner's D1 chip). + - soc: Add automatic bridging between AXI <-> AXI-Lite <-> Wishbone. + - soc: Add AXI-Full bus support. + - interconnect: Add AXI DownConverted and Interconnect/Crossbar. + - interconnect: Create axi directory and split code. + - soc: Modify SoC finalization order for more flexibility. + - soc: Add --bus-interconnect parameter to select interconect: shared/crossbar. + - valentyusb: Package and install it with LiteX. + - bios/mem_list: Align Mem Regions. + - build: Introduce GenericToolchain to cleanup/simplify build backends. + - soc/etherbone: Expose broadcast capability. + - build/lattice: Add MCLK frequency support. + - cpu/cva6: Add IRQ support. + - cores/clock: Add manual placement support to ECP5PLL. + - cores/leds: Add polarity support. + - cpu/neorv32: Switch to new NeoRV32 LiteX Core Complex and add variants support. + - cores/gpio: Add optional reset value. + - litex_client: Add --host support for remote operation. + - sim/verilator: Add jobs number support (to limit RAM usage with large SoCs/CPUs). + - soc/SocBusHandler Add get_address_width method to simplify peripheral integration. + - bios: Expose BIOS console parameters (to enable/disable history/autocomplete). + - bios: Expose BIOS LTO configuration. + - litex_json2renode: Update. + - build: Introduce YosysNextPNRToolchain to cleanup/simplify Yosys support. + - bios: Add buttons support/command. + - litex_client: Add XADC/Identifier/Leds/Buttons support to GUI. + - cpu/NaxRiscv: Update. + - build/generic_platofrm: Add add_connector methode to allow extending connectors. + - litex_server/client: Add initial information exchange between server/client. + - LitePCIe: Improve 64-bit support. - [> API changes/Deprecation + [> API changes/Deprecation -------------------------- - LiteX-Boards : Remove short import support on platforms/targets. - tools: Rename litex_gen to litex_periph_gen. - LiteX-Boards: Only generate SoC/Software headers when --build is set - Symbiflow: Rename to F4PGA. + - mkmsscimg: Rename to crcfbigen. [> 2022.04, released on May 3th 2022 ------------------------------------