From 1c5d91dce18cf128fec3d5fd85ed8d6608e4afaa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 Feb 2022 11:19:36 +0100 Subject: [PATCH] cores/jtag: Deprecate JTAG Atlantic support (Advantageously replaced by JTAG-UART). --- CHANGES | 1 + litex/soc/cores/jtag.py | 30 ------------------------------ litex/soc/integration/soc.py | 7 ------- litex/tools/litex_term.py | 7 ++----- 4 files changed, 3 insertions(+), 42 deletions(-) diff --git a/CHANGES b/CHANGES index 9272024de..b6caa1903 100644 --- a/CHANGES +++ b/CHANGES @@ -32,6 +32,7 @@ - UART "bridge" name deprecated in favor of "crossover" (already supported). - "external" CPU class support deprecated (replaced by out-of-tree support). - lxterm/lxserver/lxsim short names deprecated (used long litex_xy names). + - Deprecate JTAG-Atlantic support (Advantageously replaced by JTAG-UART). [> 2021.12, released on January 5th 2022 ---------------------------------------- diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py index a252c504f..ea640d1c8 100644 --- a/litex/soc/cores/jtag.py +++ b/litex/soc/cores/jtag.py @@ -243,36 +243,6 @@ class Cyclone10LPJTAG(AlteraJTAG): def __init__(self, reserved_pads, *args, **kwargs): AlteraJTAG.__init__(self, "cyclone10lp_jtag", reserved_pads, *args, **kwargs) -# Altera Atlantic JTAG ----------------------------------------------------------------------------- - -class JTAGAtlantic(Module): - def __init__(self): - self.sink = sink = stream.Endpoint([("data", 8)]) - self.source = source = stream.Endpoint([("data", 8)]) - - # # # - - self.specials += Instance("alt_jtag_atlantic", - # Parameters - p_LOG2_RXFIFO_DEPTH = "5", # FIXME: expose? - p_LOG2_TXFIFO_DEPTH = "5", # FIXME: expose? - p_SLD_AUTO_INSTANCE_INDEX = "YES", - - # Clk/Rst - i_clk = ClockSignal("sys"), - i_rst_n = ~ResetSignal("sys"), - - # TX - i_r_dat = sink.data, - i_r_val = sink.valid, - o_r_ena = sink.ready, - - # RX - o_t_dat = source.data, - i_t_dav = source.ready, - o_t_ena = source.valid, - ) - # Xilinx JTAG -------------------------------------------------------------------------------------- class XilinxJTAG(Module): diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 2a75539a2..e8d4186c5 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1166,7 +1166,6 @@ class LiteXSoC(SoC): supported_uarts = [ "crossover", "crossover+uartbone", - "jtag_atlantic", "jtag_uart", "sim", "stub", @@ -1199,12 +1198,6 @@ class LiteXSoC(SoC): self.add_uartbone(baudrate=baudrate) uart = UARTCrossover(**uart_kwargs) - # JTAG Atlantic. - elif uart_name in ["jtag_atlantic"]: - from litex.soc.cores.jtag import JTAGAtlantic - uart_phy = JTAGAtlantic() - uart = UART(uart_phy, **uart_kwargs) - # JTAG UART. elif uart_name in ["jtag_uart"]: from litex.soc.cores.jtag import JTAGPHY diff --git a/litex/tools/litex_term.py b/litex/tools/litex_term.py index f391e1b4f..bf72d390e 100755 --- a/litex/tools/litex_term.py +++ b/litex/tools/litex_term.py @@ -616,7 +616,7 @@ def _get_args(): parser.add_argument("--base-address", default=None, help="CSR base address.") parser.add_argument("--crossover-name", default="uart_xover", help="Crossover UART name to use (present in design/csr.csv).") - parser.add_argument("--jtag-name", default="jtag_uart", help="JTAG UART type (jtag_uart or jtag_atlantic).") + parser.add_argument("--jtag-name", default="jtag_uart", help="JTAG UART type (jtag_uart).") parser.add_argument("--jtag-config", default="openocd_xc7_ft2232.cfg", help="OpenOCD JTAG configuration file for jtag_uart.") parser.add_argument("--jtag-chain", default=1, help="JTAG chain.") return parser.parse_args() @@ -634,10 +634,7 @@ def main(): xover.open() port = os.ttyname(xover.name) elif args.port in ["jtag"]: - if args.jtag_name == "jtag_atlantic": - term.port = Nios2Terminal() - port = args.port - elif args.jtag_name == "jtag_uart": + if args.jtag_name == "jtag_uart": jtag_uart = JTAGUART(config=args.jtag_config, chain=int(args.jtag_chain)) jtag_uart.open() port = os.ttyname(jtag_uart.name)