From 1ce2073694f3bf8c210d7802db688aefd228067d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 12 Nov 2021 11:34:03 +0100 Subject: [PATCH] soc/cores/cpu/eos_s3: add interrupt support Signed-off-by: Gwenhael Goavec-Merou --- litex/soc/cores/cpu/eos_s3/core.py | 3 ++- litex/soc/integration/soc.py | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index ef5699fca..3e66770af 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -36,6 +36,7 @@ class EOS_S3(CPU): def __init__(self, platform, variant): self.platform = platform self.reset = Signal() + self.interrupt = Signal(4) self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -72,7 +73,7 @@ class EOS_S3(CPU): #SDMA_Done(), #SDMA_Active(), # FB Interrupts - #FB_msg_out(4'b0000), + i_FB_msg_out = self.interrupt, #FB_Int_Clr(8'h0), #FB_Start(), #FB_Busy= 0, diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 3687b9251..8c9d6fcb7 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -926,6 +926,11 @@ class SoC(Module): # Add Bus Masters/CSR/IRQs. if isinstance(self.cpu, cpu.EOS_S3): self.bus.add_master(master=self.cpu.wb) + if hasattr(self.cpu, "interrupt"): + self.irq.enable() + for name, loc in self.cpu.interrupts.items(): + self.irq.add(name, loc) + self.add_config("CPU_HAS_INTERRUPT") if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000, cpu.EOS_S3)): if reset_address is None: reset_address = self.mem_map["rom"]