diff --git a/examples/dataflow.py b/examples/dataflow.py
new file mode 100644
index 000000000..31aed2e1a
--- /dev/null
+++ b/examples/dataflow.py
@@ -0,0 +1,6 @@
+from migen.fhdl import verilog 
+from migen.flow.ala import *
+
+act = Divider(32)
+frag = act.get_control_fragment() + act.get_process_fragment()
+print(verilog.Convert(frag))