From 1ce4fbdb98842a44a4805802661fe031c4f64bba Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 23 Dec 2011 00:36:07 +0100 Subject: [PATCH] example: flow conversion --- examples/dataflow.py | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 examples/dataflow.py diff --git a/examples/dataflow.py b/examples/dataflow.py new file mode 100644 index 000000000..31aed2e1a --- /dev/null +++ b/examples/dataflow.py @@ -0,0 +1,6 @@ +from migen.fhdl import verilog +from migen.flow.ala import * + +act = Divider(32) +frag = act.get_control_fragment() + act.get_process_fragment() +print(verilog.Convert(frag))