From 1d1189506a5e2e03d7939c3141befa8b069790c1 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 4 Apr 2015 18:58:02 +0800
Subject: [PATCH] mibuild: support multiple specifications of include file and
 sources

---
 mibuild/altera/quartus.py   | 2 +-
 mibuild/generic_platform.py | 8 ++++----
 mibuild/xilinx/ise.py       | 2 +-
 mibuild/xilinx/vivado.py    | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py
index 49e7d77e7..0c0a99543 100644
--- a/mibuild/altera/quartus.py
+++ b/mibuild/altera/quartus.py
@@ -85,7 +85,7 @@ class AlteraQuartusToolchain:
 		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = platform.sources + [(v_file, "verilog")]
+		sources = platform.sources | {(v_file, "verilog")}
 		_build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
 		if run:
 			_run_quartus(build_name, quartus_path)
diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 4b4a6e3cf..6d3e77e8c 100644
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -184,8 +184,8 @@ class GenericPlatform:
 		if name is None:
 			name = self.__module__.split(".")[-1]
 		self.name = name
-		self.sources = []
-		self.verilog_include_paths = []
+		self.sources = set()
+		self.verilog_include_paths = set()
 		self.finalized = False
 
 	def request(self, *args, **kwargs):
@@ -229,7 +229,7 @@ class GenericPlatform:
 		if language is None:
 			language = "verilog" # default to Verilog
 		filename = os.path.abspath(filename)
-		self.sources.append((filename, language))
+		self.sources.add((filename, language))
 
 	def add_sources(self, path, *filenames, language=None):
 		for f in filenames:
@@ -251,7 +251,7 @@ class GenericPlatform:
 				self.add_source(filename, language)
 
 	def add_verilog_include_path(self, path):
-		self.verilog_include_paths.append(os.path.abspath(path))
+		self.verilog_include_paths.add(os.path.abspath(path))
 
 	def resolve_signals(self, vns):
 		# resolve signal names in constraints
diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py
index acebf6052..703e1bcca 100644
--- a/mibuild/xilinx/ise.py
+++ b/mibuild/xilinx/ise.py
@@ -149,7 +149,7 @@ class XilinxISEToolchain:
 			named_sc, named_pc = platform.resolve_signals(vns)
 			v_file = build_name + ".v"
 			tools.write_to_file(v_file, v_src)
-			sources = platform.sources + [(v_file, "verilog")]
+			sources = platform.sources | {(v_file, "verilog")}
 			if mode == "xst":
 				_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
 				isemode = "xst"
diff --git a/mibuild/xilinx/vivado.py b/mibuild/xilinx/vivado.py
index 4aabb1ea3..c2ff076c5 100644
--- a/mibuild/xilinx/vivado.py
+++ b/mibuild/xilinx/vivado.py
@@ -110,7 +110,7 @@ class XilinxVivadoToolchain:
 		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = platform.sources + [(v_file, "verilog")]
+		sources = platform.sources | {(v_file, "verilog")}
 		_build_files(platform.device, sources, platform.verilog_include_paths, build_name,
 			self.bitstream_commands, self.additional_commands)
 		tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))