From 1dddfa6841f9e40914f735d8d589d171096a24c0 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Thu, 1 Feb 2024 09:57:51 +1100
Subject: [PATCH] soc/add_spi_flash: fix default divisor and PHY_CLOCK
 calculation

Ensure default_divisor is set to desired default - 1 as required by LiteSPIClkGen
Calculate actual PHY_CLK based on default_divisor
---
 litex/soc/integration/soc.py | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 385e83da1..1031c43be 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1884,17 +1884,21 @@ class LiteXSoC(SoC):
         from litespi import LiteSPI
         from litespi.phy.generic import LiteSPIPHY
         from litespi.opcodes import SpiNorFlashOpCodes
+        import math
 
         # Checks/Parameters.
         assert mode in ["1x", "4x"]
         if clk_freq is None: clk_freq = self.sys_clk_freq
+        # From LiteSPIClkGen: clk_freq will be ``sys_clk_freq/(2*(1+div))``.
+        default_divisor = math.ceil(self.sys_clk_freq/(clk_freq*2))-1
+        clk_freq = int(self.sys_clk_freq/(2*(1+default_divisor)))
 
         # PHY.
         spiflash_phy = phy
         if spiflash_phy is None:
             self.check_if_exists(f"{name}_phy")
             spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
-            spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
+            spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=default_divisor, rate=rate)
             self.add_module(name=f"{name}_phy", module=spiflash_phy)
 
         # Core.