From 1e24fd87d1dc899ec059154e168a09421cb87dd6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 20 Sep 2021 17:34:46 +0200 Subject: [PATCH] cores/gpio: Simplify #1035. --- litex/soc/cores/gpio.py | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 649669753..b92057666 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -74,16 +74,16 @@ class GPIOInOut(Module): class GPIOTristate(_GPIOIRQ, Module, AutoCSR): def __init__(self, pads, with_irq=False): assert isinstance(pads, Signal) or isinstance(pads, Record) + nbits = len(pads) if isinstance(pads, Signal) else len(pads.o) + + self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") + self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") + self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.") # # # if isinstance(pads, Signal): - # Proper inout IOs - nbits = len(pads) - self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") - self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") - self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.") - + # Proper inout IOs. for i in range(nbits): t = TSTriple() self.specials += t.get_tristate(pads[i]) @@ -91,13 +91,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR): self.comb += t.o.eq(self._out.storage[i]) self.specials += MultiReg(t.i, self._in.status[i]) else: - # Tristate record, for external tristate IO chips or simulation - nbits = len(pads.oe) - self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") - self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") - self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.") - clocked_inputs = Signal.like(pads.i) - + # Tristate inout IOs (For external tristate IO chips or simulation). for i in range(nbits): self.comb += pads.oe[i].eq(self._oe.storage[i]) self.comb += pads.o[i].eq(self._out.storage[i])