From 1e2ad2250dc18c17c23540e861a8cbbed75a4562 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Nov 2022 19:11:15 +0100 Subject: [PATCH] compat/soc_core: Fix register_mem/rom missing imports. --- litex/compat/soc_core.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/compat/soc_core.py b/litex/compat/soc_core.py index 31de6c722..62f09ec12 100644 --- a/litex/compat/soc_core.py +++ b/litex/compat/soc_core.py @@ -67,10 +67,12 @@ class SoCCoreCompat: def register_mem(self, name, address, interface, size=0x10000000): compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)") + from litex.soc.integration.soc import SoCRegion self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size)) def register_rom(self, interface, rom_size=0xa000): compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)") + from litex.soc.integration.soc import SoCRegion self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size)) # Finalization ---------------------------------------------------------------------------------