From 1e6d1deae83a5f80f611645c2f72facd50f34b37 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Mar 2015 16:52:50 +0100 Subject: [PATCH] uart: add sim phy --- misoclib/com/uart/phy/sim.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 misoclib/com/uart/phy/sim.py diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py new file mode 100644 index 000000000..177b97ca8 --- /dev/null +++ b/misoclib/com/uart/phy/sim.py @@ -0,0 +1,18 @@ +from migen.fhdl.std import * +from migen.flow.actor import Sink, Source + +class UARTPHYSim(Module): + def __init__(self, pads): + self.dw = 8 + self.tuning_word = Signal(32) + self.sink = Sink([("d", 8)]) + self.source = Source([("d", 8)]) + + self.comb += [ + pads.source_stb.eq(self.sink.stb), + pads.source_d.eq(self.sink.d), + self.sink.ack.eq(pads.source_ack), + + self.source.stb.eq(pads.sink_stb), + self.source.d.eq(pads.sink_d) + ]