diff --git a/build.py b/build.py
index 81539374d..ef1256785 100755
--- a/build.py
+++ b/build.py
@@ -58,7 +58,7 @@ NET "asfifo*/preset_empty*" TIG;
 		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
 	plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
 	
-	plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())
+	plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
 
 if __name__ == "__main__":
 	main()