From 1eb348c573dfb68c67ed09445e5fdb5f524ac8b6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 Feb 2012 18:07:02 +0100 Subject: [PATCH] fhdl: do not attempt slicing non-array signals to keep Verilog happy --- migen/fhdl/verilog.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index f169b508f..4af82bd59 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -34,6 +34,12 @@ def _printexpr(ns, node): raise TypeError return "(" + r + ")" elif isinstance(node, _Slice): + # Verilog does not like us slicing non-array signals... + if isinstance(node.value, Signal) \ + and node.value.bv.width == 1 \ + and node.start == 0 and node.stop == 1: + return _printexpr(ns, node.value) + if node.start + 1 == node.stop: sr = "[" + str(node.start) + "]" else: