From 1f27b7405e260fe5c57374e95e7040440bf11fbc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 21 Jul 2020 19:54:42 +0200 Subject: [PATCH] soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. --- litex/soc/integration/soc.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index e7d2886d1..f258bbc07 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1299,7 +1299,10 @@ class LiteXSoC(SoC): bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width) self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness) self.comb += self.sdcore.source.connect(self.sdblock2mem.sink) - self.bus.add_master("sdblock2mem", master=bus) + if hasattr(self.cpu, "dmabus"): # FIXME: VexRiscv SMP / DMA test. + self.submodules += wishbone.Converter(bus, self.cpu.dmabus) + else: + self.bus.add_master("sdblock2mem", master=bus) self.add_csr("sdblock2mem") # Mem2Block DMA