diff --git a/litex/build/sim/core/modules/ethernet/Makefile b/litex/build/sim/core/modules/ethernet/Makefile
index 461ed86be..392ede182 100644
--- a/litex/build/sim/core/modules/ethernet/Makefile
+++ b/litex/build/sim/core/modules/ethernet/Makefile
@@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
 
 include $(SRC_DIR)/modules/rules.mak
 
-CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include
+CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
 OBJS = $(MOD).o tapcfg.o taplog.o
 
 $(MOD).so: $(OBJS)
@@ -13,8 +13,8 @@ else
 	$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
 endif
 
-tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c
+tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c
+taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
 	$(CC) $(CFLAGS) -c -o $@ $<
diff --git a/litex/build/sim/core/modules/xgmii_ethernet/Makefile b/litex/build/sim/core/modules/xgmii_ethernet/Makefile
index 461ed86be..392ede182 100644
--- a/litex/build/sim/core/modules/xgmii_ethernet/Makefile
+++ b/litex/build/sim/core/modules/xgmii_ethernet/Makefile
@@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
 
 include $(SRC_DIR)/modules/rules.mak
 
-CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include
+CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
 OBJS = $(MOD).o tapcfg.o taplog.o
 
 $(MOD).so: $(OBJS)
@@ -13,8 +13,8 @@ else
 	$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
 endif
 
-tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c
+tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c
+taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
 	$(CC) $(CFLAGS) -c -o $@ $<
diff --git a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg b/litex/build/sim/core/modules/xgmii_ethernet/tapcfg
deleted file mode 120000
index d0b6901bd..000000000
--- a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg
+++ /dev/null
@@ -1 +0,0 @@
-../ethernet/tapcfg/
\ No newline at end of file
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index f068d08d1..2fc251940 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -7,7 +7,7 @@ import sys
 import subprocess
 
 from migen.fhdl.structure import _Fragment
-
+from litex import get_data_mod
 from litex.build import tools
 from litex.build.generic_platform import *
 
@@ -102,13 +102,15 @@ extern "C" void litex_sim_init(void **out)
 
 
 def _generate_sim_variables(include_paths):
+    tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
     include = ""
     for path in include_paths:
         include += "-I"+path+" "
     content = """\
 SRC_DIR = {}
 INC_DIR = {}
-""".format(core_directory, include)
+TAPCFG_DIRECTORY = {}
+""".format(core_directory, include, tapcfg_dir)
     tools.write_to_file("variables.mak", content)