From 1f58ce3c31b9b2a396f7d9a97038ab1a0e1b8398 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 21 Oct 2022 19:39:02 +0200 Subject: [PATCH] gen/fhdl/verilog: Improve _print_signal to align signals definition. --- litex/gen/fhdl/verilog.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index e1ea8d4c7..025379a77 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -145,9 +145,12 @@ def _print_constant(node): # Print Signal ------------------------------------------------------------------------------------- def _print_signal(ns, s): + length = 8 + vector = f"[{str(len(s)-1)}:0] " + vector = " "*(length-len(vector)) + vector return "{signed}{vector}{name}".format( - signed = "" if (not s.signed) else "signed ", - vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ", + signed = " " if (not s.signed) else "signed ", + vector = " "*length if (len(s) <= 1) else vector, name = ns.get_name(s) )