From 1f7549b4c0f7487ec5af94a32008c8c5004194a5 Mon Sep 17 00:00:00 2001 From: bunnie Date: Fri, 24 Jan 2020 15:01:13 +0800 Subject: [PATCH] add BUFIO to clockgen buffer options --- litex/soc/cores/clock.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 3d427bcff..5e62f5de7 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -59,6 +59,8 @@ class XilinxClocking(Module, AutoCSR): self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf) elif buf == "bufgce" and clk_ce != None: self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce) + elif buf == "bufio": + self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf) else: raise ValueError