diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index a63c5d6c9..dc2e7fb7b 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -731,7 +731,7 @@ class SoC(Module):
         self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
         self.logger.info(colorer("-"*80, color="bright"))
         self.logger.info("FPGA device : {}.".format(platform.device))
-        self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6))
+        self.logger.info("System clock: {:3.3f}MHz.".format(sys_clk_freq/1e6))
 
         # SoC attributes ---------------------------------------------------------------------------
         self.platform     = platform