From 20207c9c320308dd99aeb09cd986ac3b6d9b5ba9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 22 Mar 2015 11:08:47 +0100 Subject: [PATCH] liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6) --- misoclib/com/liteusb/common.py | 4 ++-- misoclib/com/liteusb/core/__init__.py | 8 ++++---- misoclib/com/liteusb/core/com.py | 22 ++++++++++------------ misoclib/com/liteusb/core/crc.py | 2 +- misoclib/com/liteusb/core/depacketizer.py | 6 +++--- misoclib/com/liteusb/core/packetizer.py | 4 ++-- misoclib/com/liteusb/frontend/crossbar.py | 4 ++-- misoclib/com/liteusb/frontend/dma.py | 10 +++++----- misoclib/com/liteusb/frontend/uart.py | 2 +- misoclib/com/liteusb/phy/ft2232h.py | 12 ++++++------ 10 files changed, 36 insertions(+), 38 deletions(-) diff --git a/misoclib/com/liteusb/common.py b/misoclib/com/liteusb/common.py index e1cf05aa1..e660137f4 100644 --- a/misoclib/com/liteusb/common.py +++ b/misoclib/com/liteusb/common.py @@ -16,12 +16,12 @@ phy_layout = [ ("d", 8) ] -class FtdiPipe: +class LiteUSBPipe: def __init__(self, layout): self.sink = Sink(layout) self.source = Source(layout) -class FtdiTimeout(Module): +class LiteUSBTimeout(Module): def __init__(self, clk_freq, length): cnt_max = int(clk_freq*length) width = bits_for(cnt_max) diff --git a/misoclib/com/liteusb/core/__init__.py b/misoclib/com/liteusb/core/__init__.py index 42b2ee4b2..d3b6c0686 100644 --- a/misoclib/com/liteusb/core/__init__.py +++ b/misoclib/com/liteusb/core/__init__.py @@ -1,4 +1,4 @@ -from misoclib.com.liteusb.frontend.uart import FtdiUART -from misoclib.com.liteusb.frontend.dma import FtdiDMA -from misoclib.com.liteusb.core.com import FtdiCom -from misoclib.com.liteusb.core.crc import FtdiCRC32 +from misoclib.com.liteusb.frontend.uart import LiteUSBUART +from misoclib.com.liteusb.frontend.dma import LiteUSBDMA +from misoclib.com.liteusb.core.com import LiteUSBCom +from misoclib.com.liteusb.core.crc import LiteUSBCRC32 diff --git a/misoclib/com/liteusb/core/com.py b/misoclib/com/liteusb/core/com.py index e016638a8..826cf5d51 100644 --- a/misoclib/com/liteusb/core/com.py +++ b/misoclib/com/liteusb/core/com.py @@ -2,27 +2,25 @@ from migen.fhdl.std import * from migen.flow.actor import * from misoclib.com.liteusb.common import * -from misoclib.com.liteusb.frontend.crossbar import FtdiCrossbar -from misoclib.com.liteusb.core.packetizer import FtdiPacketizer -from misoclib.com.liteusb.core.depacketizer import FtdiDepacketizer -from misoclib.com.liteusb.phy.ft2232h import FtdiPHY +from misoclib.com.liteusb.frontend.crossbar import LiteUSBCrossbar +from misoclib.com.liteusb.core.packetizer import LiteUSBPacketizer +from misoclib.com.liteusb.core.depacketizer import LiteUSBDepacketizer -class FtdiCom(Module): - def __init__(self, pads, *ports): +class LiteUSBCom(Module): + def __init__(self, phy, *ports): # crossbar - self.submodules.crossbar = FtdiCrossbar(list(ports)) + self.submodules.crossbar = LiteUSBCrossbar(list(ports)) # packetizer / depacketizer - self.submodules.packetizer = FtdiPacketizer() - self.submodules.depacketizer = FtdiDepacketizer() + self.submodules.packetizer = LiteUSBPacketizer() + self.submodules.depacketizer = LiteUSBDepacketizer() self.comb += [ self.crossbar.slave.source.connect(self.packetizer.sink), self.depacketizer.source.connect(self.crossbar.slave.sink) ] # phy - self.submodules.phy = FtdiPHY(pads) self.comb += [ - self.packetizer.source.connect(self.phy.sink), - self.phy.source.connect(self.depacketizer.sink) + self.packetizer.source.connect(phy.sink), + phy.source.connect(self.depacketizer.sink) ] diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py index 26fb76074..dfbb5c311 100644 --- a/misoclib/com/liteusb/core/crc.py +++ b/misoclib/com/liteusb/core/crc.py @@ -283,7 +283,7 @@ class CRC32Checker(CRCChecker): def __init__(self, layout): CRCChecker.__init__(self, CRC32, layout) -class FtdiCRC32(Module): +class LiteUSBCRC32(Module): def __init__(self, tag): self.tag = tag diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py index 97400df3e..a6b0e18a1 100644 --- a/misoclib/com/liteusb/core/depacketizer.py +++ b/misoclib/com/liteusb/core/depacketizer.py @@ -4,7 +4,7 @@ from migen.genlib.fsm import FSM, NextState from misoclib.com.liteusb.common import * -class FtdiDepacketizer(Module): +class LiteUSBDepacketizer(Module): def __init__(self, timeout=10): self.sink = sink = Sink(phy_layout) self.source = source = Source(user_layout) @@ -53,7 +53,7 @@ class FtdiDepacketizer(Module): header_pack.source.ack.eq(1), ) - self.submodules.timeout = FtdiTimeout(60000000, timeout) + self.submodules.timeout = LiteUSBTimeout(60000000, timeout) self.comb += self.timeout.clear.eq(fsm.ongoing("WAIT_SOP")) fsm.act("RECEIVE_HEADER", @@ -137,7 +137,7 @@ class DepacketizerSinkModel(Module, Sink, RandRun): class TB(Module): def __init__(self): self.submodules.source = DepacketizerSourceModel(src_data) - self.submodules.dut = FtdiDepacketizer() + self.submodules.dut = LiteUSBDepacketizer() self.submodules.sink = DepacketizerSinkModel() self.comb += [ diff --git a/misoclib/com/liteusb/core/packetizer.py b/misoclib/com/liteusb/core/packetizer.py index de9c69ed4..6926aa697 100644 --- a/misoclib/com/liteusb/core/packetizer.py +++ b/misoclib/com/liteusb/core/packetizer.py @@ -4,7 +4,7 @@ from migen.genlib.fsm import FSM, NextState from misoclib.com.liteusb.common import * -class FtdiPacketizer(Module): +class LiteUSBPacketizer(Module): def __init__(self): self.sink = sink = Sink(user_layout) self.source = source = Source(phy_layout) @@ -132,7 +132,7 @@ class PacketizerSinkModel(Module, Sink, RandRun): class TB(Module): def __init__(self): self.submodules.source = PacketizerSourceModel(src_data) - self.submodules.dut = FtdiPacketizer() + self.submodules.dut = LiteUSBPacketizer() self.submodules.sink = PacketizerSinkModel() self.comb +=[ diff --git a/misoclib/com/liteusb/frontend/crossbar.py b/misoclib/com/liteusb/frontend/crossbar.py index cc548a43a..5f57abaed 100644 --- a/misoclib/com/liteusb/frontend/crossbar.py +++ b/misoclib/com/liteusb/frontend/crossbar.py @@ -4,10 +4,10 @@ from migen.genlib.record import Record from misoclib.com.liteusb.common import * -class FtdiCrossbar(Module): +class LiteUSBCrossbar(Module): def __init__(self, masters, slave=None): if slave is None: - slave = FtdiPipe(user_layout) + slave = LiteUSBPipe(user_layout) self.slave = slave # masters --> slave arbitration diff --git a/misoclib/com/liteusb/frontend/dma.py b/misoclib/com/liteusb/frontend/dma.py index bcbbe4fbc..4768d5b54 100644 --- a/misoclib/com/liteusb/frontend/dma.py +++ b/misoclib/com/liteusb/frontend/dma.py @@ -10,7 +10,7 @@ from misoclib.mem.sdram.frontend import dma_lasmi from misoclib.com.liteusb.common import * -class FtdiDMAWriter(Module, AutoCSR): +class LiteUSBDMAWriter(Module, AutoCSR): def __init__(self, lasmim): self.sink = sink = Sink(user_layout) @@ -50,7 +50,7 @@ class FtdiDMAWriter(Module, AutoCSR): self._crc_failed.status.eq(sink.error) ) -class FtdiDMAReader(Module, AutoCSR): +class LiteUSBDMAReader(Module, AutoCSR): def __init__(self, lasmim, tag): self.source = source = Source(user_layout) @@ -89,12 +89,12 @@ class FtdiDMAReader(Module, AutoCSR): self.ev.finalize() self.comb += self.ev.done.trigger.eq(source.stb & source.eop) -class FtdiDMA(Module, AutoCSR): +class LiteUSBDMA(Module, AutoCSR): def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag): self.tag = tag - self.submodules.writer = FtdiDMAWriter(lasmim_ftdi_dma_wr) - self.submodules.reader = FtdiDMAReader(lasmim_ftdi_dma_rd, self.tag) + self.submodules.writer = LiteUSBDMAWriter(lasmim_ftdi_dma_wr) + self.submodules.reader = LiteUSBDMAReader(lasmim_ftdi_dma_rd, self.tag) self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev) self.sink = self.writer.sink diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py index 2712d7b93..a490dbc02 100644 --- a/misoclib/com/liteusb/frontend/uart.py +++ b/misoclib/com/liteusb/frontend/uart.py @@ -5,7 +5,7 @@ from migen.genlib.fifo import SyncFIFOBuffered from misoclib.com.liteusb.common import * -class FtdiUART(Module, AutoCSR): +class LiteUSBUART(Module, AutoCSR): def __init__(self, tag, fifo_depth=64): self.tag = tag diff --git a/misoclib/com/liteusb/phy/ft2232h.py b/misoclib/com/liteusb/phy/ft2232h.py index 05b9cedd1..9ae35ba52 100644 --- a/misoclib/com/liteusb/phy/ft2232h.py +++ b/misoclib/com/liteusb/phy/ft2232h.py @@ -5,7 +5,7 @@ from migen.fhdl.specials import * from misoclib.com.liteusb.common import * -class FtdiPHY(Module): +class FT2232HPHY(Module): def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16): dw = flen(pads.data) @@ -152,7 +152,7 @@ class FtdiPHY(Module): # # TB # -class FtdiModel(Module, RandRun): +class FT2232HModel(Module, RandRun): def __init__(self, rd_data): RandRun.__init__(self, 50) self.rd_data = [0] + rd_data @@ -258,8 +258,8 @@ user_wr_data = [i%256 for i in range(LENGTH)] class TB(Module): def __init__(self): - self.submodules.model = FtdiModel(model_rd_data) - self.submodules.phy = FtdiPHY(self.model) + self.submodules.model = FT2232HModel(model_rd_data) + self.submodules.phy = FT2232HPHY(self.model) self.submodules.user = UserModel(user_wr_data) @@ -305,8 +305,8 @@ def main(): #print(len(tb.user.rd_data)) #print(len(tb.model.wr_data)) - print_results("FtdiModel --> UserModel", model_rd_data, tb.user.rd_data) - print_results("UserModel --> FtdiModel", user_wr_data, tb.model.wr_data) + print_results("F2232HModel --> UserModel", model_rd_data, tb.user.rd_data) + print_results("UserModel --> FT2232HModel", user_wr_data, tb.model.wr_data) if __name__ == "__main__": main()