From 2024542a3c8d14c9daeb53c912cd0bda43f73abc Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 28 Jun 2018 09:24:34 +0800 Subject: [PATCH] vexriscv: verilog: pull debug-enabled verilog The upstream vexriscv repo now generates both the current VexRiscv.v softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes their specialized debug bus that allows for attaching a modified version of openocd. Sync the litex repo with the upstream version to take advantage of debug support. Signed-off-by: Sean Cross --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 4811a1212..395c5ee28 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb +Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5