From 206118c427f3d68690b48850a1604a00d6c625df Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 28 Mar 2024 09:16:25 +0100
Subject: [PATCH] Add missing file

---
 litex/soc/cores/cpu/vexiiriscv/system.h | 55 +++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 litex/soc/cores/cpu/vexiiriscv/system.h

diff --git a/litex/soc/cores/cpu/vexiiriscv/system.h b/litex/soc/cores/cpu/vexiiriscv/system.h
new file mode 100644
index 000000000..38c7abe9a
--- /dev/null
+++ b/litex/soc/cores/cpu/vexiiriscv/system.h
@@ -0,0 +1,55 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#include <csr-defs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((unused)) static void flush_cpu_icache(void)
+{
+  asm volatile(
+    "fence.i\n"
+  );
+}
+
+__attribute__((unused)) static void flush_cpu_dcache(void)
+{
+  //asm volatile(".word(0x500F)\n");
+}
+
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+void busy_wait_us(unsigned int us);
+
+#include <csr-defs.h>
+
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+  asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+  asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+  asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+  asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+  asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+  asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */