diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py
new file mode 100644
index 000000000..ca8200a18
--- /dev/null
+++ b/examples/basic/local_cd.py
@@ -0,0 +1,17 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.fhdl import verilog
+from migen.genlib.divider import Divider
+
+class CDM(Module):
+	def __init__(self):
+		self.submodules.divider = Divider(5)
+		self.clock_domains.cd_sys = ClockDomain()
+
+class MultiMod(Module):
+	def __init__(self):
+		self.submodules.foo = CDM()
+		self.submodules.bar = CDM()
+
+mm = MultiMod()
+print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))