From 20d87682adf1533bd9651e7b97683539c8c5a8f9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 23 Nov 2012 13:10:40 +0100 Subject: [PATCH] examples/pytholite/uio: simulate and convert Pytholite --- examples/pytholite/uio.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/examples/pytholite/uio.py b/examples/pytholite/uio.py index c4b62eca0..e3572b569 100644 --- a/examples/pytholite/uio.py +++ b/examples/pytholite/uio.py @@ -13,8 +13,9 @@ layout = [("r", BV(32))] def gen(): ds = Register(32) - for i in range(10): - r = TRead(i) + for i in range(5): + # NB: busname is optional when only one bus is configured + r = TRead(i, busname="wb") yield r ds.store = r.data yield Token("result", {"r": ds}) @@ -55,11 +56,13 @@ def main(): buses={"wb": wishbone.Interface()}) run_sim(ng_native) - #print("Simulating Pytholite:") - #ng_pytholite = make_pytholite(gen, dataflow=[("result", Source, layout)]) - #run_sim(ng_pytholite) + print("Simulating Pytholite:") + ng_pytholite = make_pytholite(gen, + dataflow=[("result", Source, layout)], + buses={"wb": wishbone.Interface()}) + run_sim(ng_pytholite) - #print("Converting Pytholite to Verilog:") - #print(verilog.convert(ng_pytholite.get_fragment())) + print("Converting Pytholite to Verilog:") + print(verilog.convert(ng_pytholite.get_fragment())) main()