From 20ed23443b16f51f65b70b8c2a5b79fc3d273b5a Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Sun, 21 Jan 2018 21:46:01 +0000 Subject: [PATCH] Export trap signal from PicoRV32. This is useful for handling crashes from hardware. --- litex/soc/cores/cpu/picorv32/core.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 3e9464366..6d20a9d04 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -6,10 +6,11 @@ from litex.soc.interconnect import wishbone class PicoRV32(Module): - def __init__(self, platform, progaddr_reset): + def __init__(self, platform, progaddr_reset, variant): self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) + self.trap = Signal() # # # @@ -51,7 +52,7 @@ class PicoRV32(Module): i_resetn=~ResetSignal(), # trap - o_trap=Signal(), # not used + o_trap=self.trap, # memory interface o_mem_valid=mem_valid,