diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py
index e4cfbc38f..4eec9cdb9 100755
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@@ -439,6 +439,16 @@ class VexiiRiscv(CPU):
         )
         self.memory_buses.append(mbus)
 
+        self.comb += mbus.aw.cache.eq(0xF)
+        self.comb += mbus.aw.lock.eq(0)
+        self.comb += mbus.aw.prot.eq(1)
+        self.comb += mbus.aw.qos.eq(0)
+
+        self.comb += mbus.ar.cache.eq(0xF)
+        self.comb += mbus.ar.lock.eq(0)
+        self.comb += mbus.ar.prot.eq(1)
+        self.comb += mbus.ar.qos.eq(0)
+
         self.cpu_params.update(
             # Memory Bus (Master).
             # --------------------