From 220f43753ba13554cddea984c7a0f8a6e9e21424 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Jul 2019 16:51:08 +0200 Subject: [PATCH] soc_zynq: add missing axi hp0 clock --- litex/soc/integration/soc_zynq.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py index 0c237a65c..f8b1784f4 100644 --- a/litex/soc/integration/soc_zynq.py +++ b/litex/soc/integration/soc_zynq.py @@ -138,6 +138,9 @@ class SoCZynq(SoCCore): self.axi_hp0 = axi_hp0 = axi.AXIInterface(data_width=64, address_width=32, id_width=6) self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout()) self.ps7_params.update( + # axi hp0 clk + i_M_AXI_HP0_ACLK=ClockSignal("sys"), + # axi hp0 aw i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid, o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,